 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Users Man u a l , Versi o n 2 .1 , Jun e 2 0 0 0 S DA 6 0 0 0 Tel e t e x t Dec oder w i t h E m b e d d e d 16-bi t C o n t r o lle r M2 IC s fo r Cons um e r s Never stop thinking. Edition 2000-06-15 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2000. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Contents Overview Pin Description Architectural Overview C16X Microcontroller Interrupt and Trap Function System Control & Configuration Peripherals Clock System Sync System Display Generator D/A Converter Slicer and Acquisition Register Overview Elelctrical Characteristics Users Man u a l , Versi o n 2 .1 , Jun e 2 0 0 0 SDA 6000 Te l e t ex t Dec od e r w i t h E m b e d de d 16 -bi t Cont rolle r IC s fo r Cons um e r s Never stop thinking. SDA 6000 Revision History: Previous Version: Page Current Version: 2000-06-15 08.99 Subjects (major changes since last revision) Complete Update of Controller & Peripheral Spec --> Detailed Version ASC: Autobaud Detection Feature included IC: New Description GPT: New Description IIC changed to I2C For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com Contents Overview SDA 6000 Table of Contents 1 1.1 1.2 2 2.1 2.2 3 4 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 4.6 4.6.1 4.6.2 4.6.3 4.6.4 5 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.3 5.3.1 Page Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3 Pin Diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 4 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3 C16X Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 3 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 5 On-Chip Microcontroller RAM and SFR Area . . . . . . . . . . . . . . . . . . . . 4 - 7 System Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 9 PEC Source and Destination Pointers . . . . . . . . . . . . . . . . . . . . . . . 4 - 10 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11 External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 12 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13 External Static Memory Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13 External Bus Interface (EBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 13 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 16 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 19 Crossing Memory Boundaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 23 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 24 Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 26 Bit-Handling and Bit-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 32 Instruction State Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 33 CPU Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 34 Interrupt and Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 Interrupt System Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 3 Interrupt Allocation Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 4 Hardware Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 6 Operation of the PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 13 Prioritization of Interrupt and PEC Service Requests . . . . . . . . . . . 5 - 20 Saving the Status during Interrupt Service . . . . . . . . . . . . . . . . . . . 5 - 22 Interrupt Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 23 PEC Response Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 25 Fast Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 27 Trap Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 28 External Interrupt Source Control . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33 Users Manual i-3 2000-06-15 SDA 6000 Table of Contents 6 6.1 6.1.1 6.1.2 6.1.3 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.9.1 6.9.2 6.10 7 7.1 7.1.1 7.1.1.1 7.1.2 7.1.2.1 7.1.2.2 7.1.2.3 7.1.3 7.1.4 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.2 7.3.2.1 7.3.2.2 7.3.2.3 7.3.3 7.3.3.1 7.3.3.2 7.3.4 Page System Control & Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 3 Behavior of I/Os during Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5 Reset Values for the Controller Core Registers . . . . . . . . . . . . . . . . . 6 - 5 The Internal RAM after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5 System Start-up Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 5 Register Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 8 Power Reduction Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 12 Dedicated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 15 XBUS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 17 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 17 Bootstrap Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 21 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 23 System Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 23 CPU Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 26 Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 27 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 3 Functional Description of Timer Block 1 . . . . . . . . . . . . . . . . . . . . . . 7 - 3 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 14 Functional Description of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . 7 - 19 Core Timer T6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 20 Auxiliary Timer T5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 21 Timer Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 22 GPT Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 26 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 37 Real-time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 39 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 39 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 41 Asynchronous/Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . 7 - 46 Asynchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 49 Asynchronous Data Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 51 Asynchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 53 Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 54 Synchronous Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 56 Synchronous Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 57 Synchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 58 Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 58 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 59 Baud Rates in Asynchronous Mode . . . . . . . . . . . . . . . . . . . . . . 7 - 60 Baud Rates in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . 7 - 63 Autobaud Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 63 i-4 2000-06-15 Users Manual SDA 6000 Table of Contents 7.3.4.1 7.3.4.2 7.3.4.3 7.3.5 7.3.6 7.3.7 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.6 7.6.1 7.6.2 8 8.1 8.2 9 9.1 9.1.1 9.1.2 9.2 10 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.4 10.4.1 10.4.2 10.5 Page Serial Frames for Autobaud Detection . . . . . . . . . . . . . . . . . . . . . 7 - 64 Baud Rate Selection and Calculation . . . . . . . . . . . . . . . . . . . . . 7 - 67 Overwriting Registers on Successful Autobaud Detection . . . . . 7 - 69 ASC Hardware Error Detection Capabilities . . . . . . . . . . . . . . . . . . 7 - 70 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 71 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 72 High Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . 7 - 82 Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 86 Half Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 89 Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 90 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 91 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 91 Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 92 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 95 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 99 Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 100 The Physical I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 100 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 103 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 105 Analog Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 118 Power Down and Wake Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 119 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 119 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3 General Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 4 Sync System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Screen Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sync Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9-3 9-3 9-5 9-6 Display Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3 Screen Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 3 Layer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5 Overlapped Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 6 Embedded Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 8 Transparency in Screen Background Area . . . . . . . . . . . . . . . . . . . 10 - 9 Input and Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 11 Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 12 Output Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13 Initialization of Memory Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17 i-5 2000-06-15 Users Manual SDA 6000 Table of Contents 10.5.1 10.5.2 10.5.3 10.6 10.6.1 10.7 10.7.1 10.7.2 10.7.3 10.7.4 10.7.5 10.7.6 10.7.7 10.7.8 10.7.9 10.7.10 10.7.11 10.7.12 10.7.13 11 11.1 12 12.1 12.2 12.2.1 12.2.2 12.3 12.4 12.4.1 12.4.2 12.4.3 12.5 12.5.1 12.5.2 13 13.1 13.2 13.3 13.4 13.4.1 13.4.2 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Italic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Description of Graphic Accelerator Instructions . . . . . . . . . . . . . . . . . Screen Attributes (SAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startaddress of Layer 1 (FBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Size of Layer 1 (FSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startaddress of Layer 2 (DBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . Size of Layer 2 (DSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Display Coordinates of Layer 2 (DCR) . . . . . . . . . . . . . . . . . . . . . Contents of CLUT (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clipping Coordinates (CUR and CBR) . . . . . . . . . . . . . . . . . . . . . . Source Descriptor for Data Transfer (SDR) . . . . . . . . . . . . . . . . . . Source Size of Transferred Memory Area (TSR) . . . . . . . . . . . . . . Destination Size of Transferred Memory Area (TDR) . . . . . . . . . . Offset of Transferred Memory Area (TOR) . . . . . . . . . . . . . . . . . . Attributes of Transfer (TAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 10 - 17 10 - 20 10 - 25 10 - 27 10 - 27 10 - 30 10 - 32 10 - 35 10 - 35 10 - 36 10 - 36 10 - 37 10 - 38 10 - 38 10 - 40 10 - 41 10 - 42 10 - 43 10 - 44 D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 3 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 - 3 Slicer and Acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 3 General Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 3 Slicer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 3 Distortion Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 5 Data Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6 H/V-Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6 Acquisition Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 6 FC-Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 8 VBI Buffer and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . 12 - 8 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 9 RAM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 12 Recommended Parameter Settings . . . . . . . . . . . . . . . . . . . . . . . . 12 - 25 Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 3 Register Description Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 3 CPU General Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . 13 - 4 Registers ordered by Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 5 Registers Ordered by Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 13 Registers in SFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 14 Registers in ESFR Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 - 15 i-6 2000-06-15 Users Manual SDA 6000 Table of Contents 14 14.1 14.2 14.3 14.4 14.5 Page Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 3 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 4 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 - 11 Users Manual i-7 2000-06-15 SDA 6000 List of Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 3-1 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13 Figure 4-14 Figure 4-15 Figure 4-16 Figure 4-17 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Figure 7-11 Users Manual Page M2 Tool Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 5 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 - 3 M2 Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 - 3 M2 Memory Path Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 6 Storage of Words, Byte and Bits in a Byte Organized Memory . . . . 4 - 7 Internal RAM Areas and SFR Areas . . . . . . . . . . . . . . . . . . . . . . . . 4 - 8 Location of the PEC Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 11 External Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 14 Interlocked Access Cycles to ROM and SDRAM. . . . . . . . . . . . . . 4 - 15 Interlocked Access Cycles to two SDRAM Banks . . . . . . . . . . . . . 4 - 16 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 17 Four-Phase Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 21 CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 25 Sequential Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . 4 - 28 Standard Branch Instruction Pipelining . . . . . . . . . . . . . . . . . . . . . 4 - 28 Cache Jump Instruction Pipelining. . . . . . . . . . . . . . . . . . . . . . . . . 4 - 29 Addressing via the Code Segment Pointer . . . . . . . . . . . . . . . . . . 4 - 42 Addressing via the Data Page Pointers . . . . . . . . . . . . . . . . . . . . . 4 - 44 Register Bank Selection via Register CP. . . . . . . . . . . . . . . . . . . . 4 - 45 Implicit CP Use by Short GPR Addressing Modes. . . . . . . . . . . . . 4 - 46 Priority Levels and PEC Channels . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 10 Mapping of PEC Offset Pointers into the Internal RAM . . . . . . . . . 5 - 19 Task Status Saved on the System Stack . . . . . . . . . . . . . . . . . . . . 5 - 22 Pipeline Diagram for Interrupt Response Time . . . . . . . . . . . . . . . 5 - 23 Pipeline Diagram for PEC Response Time . . . . . . . . . . . . . . . . . . 5 - 26 State Machine for Security Level Switching . . . . . . . . . . . . . . . . . . 6 - 11 Transitions between Idle Mode and Active Mode . . . . . . . . . . . . . 6 - 14 WDT Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 18 Bootstrap Loader Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 22 Portlogic Register Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 - 27 Structure of Timer Block 1 Core Timer T3 . . . . . . . . . . . . . . . . . . . . 7 - 4 Block Diagram of Core Timer T3 in Timer Mode . . . . . . . . . . . . . . . 7 - 7 Block Diagram of Core Timer T3 in Gated Timer Mode. . . . . . . . . . 7 - 7 Block Diagram of Core Timer T3 in Counter Mode . . . . . . . . . . . . . 7 - 8 Block Diagram of Core Timer T3 in Incremental Interface Mode . . . 7 - 9 Interfacing the Encoder to the Microcontroller . . . . . . . . . . . . . . . . 7 - 10 Evaluation of the Incremental Encoder Signals . . . . . . . . . . . . . . . 7 - 11 Evaluation of the Incremental Encoder Signals . . . . . . . . . . . . . . . 7 - 12 Block Diagram of an Auxiliary Timer in Counter Mode . . . . . . . . . 7 - 13 Concatenation of Core Timer T3 and an Auxiliary Timer . . . . . . . . 7 - 15 GPT1 Auxiliary Timer in Reload Mode. . . . . . . . . . . . . . . . . . . . . . 7 - 16 f-1 2000-06-15 SDA 6000 List of Figures Figure 7-12 Figure 7-13 Figure 7-14 Figure 7-15 Figure 7-16 Figure 7-17 Figure 7-18 Figure 7-19 Figure 7-20 Figure 7-21 Figure 7-22 Figure 7-23 Figure 7-24 Figure 7-25 Figure 7-26 Figure 7-27 Figure 7-28 Figure 7-29 Figure 7-30 Figure 7-31 Figure 7-32 Figure 7-33 Figure 7-34 Figure 7-35 Figure 7-36 Figure 7-37 Figure 7-38 Figure 7-39 Figure 7-40 Figure 7-41 Figure 7-42 Figure 7-43 Figure 7-44 Figure 7-45 Figure 7-46 Figure 7-47 Figure 8-1 Figure 9-1 Figure 9-2 Figure 10-1 Page GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . 7 - 17 Auxiliary Timer of Timer Block 1 in Capture Mode. . . . . . . . . . . . . 7 - 18 Structure of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19 Block Diagram of Core Timer T6 in Timer Mode . . . . . . . . . . . . . . 7 - 21 Concatenation of Core Timer T6 and Auxiliary Timer T5. . . . . . . . 7 - 22 Timer Block 2 Register CAPREL in Capture Mode . . . . . . . . . . . . 7 - 23 Timer Block 2 Register CAPREL in Reload Mode . . . . . . . . . . . . . 7 - 24 Timer Block 2 Register CAPREL in Capture-And-Reload Mode . . 7 - 25 RTC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 39 RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 40 Block Diagram of the ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 47 ASC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 48 Asynchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . 7 - 50 Asynchronous 8-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 51 Asynchronous 9-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 52 IrDA Frame Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 53 Fixed IrDA Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 55 RXD/TXD Data Path in Asynchronous Modes . . . . . . . . . . . . . . . . 7 - 56 Synchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . . 7 - 57 ASC0 Synchronous Mode Waveforms. . . . . . . . . . . . . . . . . . . . . . 7 - 59 ASC0 Baud Rate Generator Circuitry in Asynchronous Modes . . . 7 - 61 ASC0 Baud Rate Generator Circuitry in Synchronous Mode. . . . . 7 - 63 ASC_P3 Asynchronous Mode Block Diagram . . . . . . . . . . . . . . . . 7 - 64 Two-Byte Serial Frames with ASCII `at' . . . . . . . . . . . . . . . . . . . . . 7 - 65 Two-Byte Serial Frames with ASCII `AT' . . . . . . . . . . . . . . . . . . . . 7 - 66 ASC0 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 72 SFRs and Port Pins Associated with the SSC0 . . . . . . . . . . . . . . . 7 - 83 Synchronous Serial Channel SSC0 Block Diagram. . . . . . . . . . . . 7 - 84 Serial Clock Phase and Polarity Options . . . . . . . . . . . . . . . . . . . . 7 - 86 SSC0 Full Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 87 SSC Half Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 90 SSC0 Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 91 SSC0 Error Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 93 I2C Bus Line Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 100 Physical Bus Configuration Example . . . . . . . . . . . . . . . . . . . . . . 7 - 102 SFRs and Port Pins Associated with the A/D Converter . . . . . . . 7 - 118 Clock System in M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3 M2's Display Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4 Priority of Clamp Phase, Screen Background and Pixel Layer Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11 Display Regions and Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4 Users Manual f-2 2000-06-15 SDA 6000 List of Figures Figure 10-2 Figure 10-3 Figure 10-4 Figure 10-5 Figure 10-6 Figure 10-7 Figure 10-8 Figure 10-9 Figure 10-10 Figure 10-11 Figure 10-12 Figure 10-13 Figure 10-14 Figure 10-15 Figure 10-16 Figure 10-17 Figure 10-18 Figure 10-19 Figure 10-20 Figure 10-21 Figure 10-22 Figure 12-1 Figure 12-2 Figure 14-1 Figure 14-2 Page Behavior of Blank Pin for Consecutive Frames in `Meshed' Regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 5 Priority of Layers in Overlapped Layer Mode. . . . . . . . . . . . . . . . . 10 - 6 Priority of Layers in Embedded Layer Mode . . . . . . . . . . . . . . . . . 10 - 9 Format of 1-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 12 Format of 2-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 12 Format of 4-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 12 Format of 8-bitplane Bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13 Overview on SRU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 13 2-bit Pixel Format for Use in Frame Buffer. . . . . . . . . . . . . . . . . . 10 - 14 8-bit Pixel Format for Use in Frame Buffer. . . . . . . . . . . . . . . . . . 10 - 14 16-bit Pixel Format (4:4:4:2/TTX) for Use in Frame Buffer . . . . . 10 - 15 Internally Generated Flash Signals in Different Flash Phases. . . 10 - 16 16-bit Pixel Format (5:6:5) for Use in Frame Buffer . . . . . . . . . . . 10 - 16 Overview of GA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 17 Use of Register Settings to Specify Source Area. . . . . . . . . . . . . 10 - 22 Use of Register Settings to Specify Destination and Clipping Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 25 Result for a Non-italic Transferred Memory Area in Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 25 Result for a Italic Transferred Memory Area in Frame Buffer . . . 10 - 26 Result for an Italic Transferred Memory Area at D/A Converter Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 26 Organization of GAIs in the External SDRAM . . . . . . . . . . . . . . . 10 - 30 GAI Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 31 Block Diagram of Digital Slicer and Acquisition Interface . . . . . . . 12 - 4 VBI Buffer: General Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 - 9 H/V - Sync-Timing (Sync-master mode) . . . . . . . . . . . . . . . . . . . 14 - 10 VCS -Timing (Sync-master mode) . . . . . . . . . . . . . . . . . . . . . . . . 14 - 10 Users Manual f-3 2000-06-15 SDA 6000 Preface M2 is a 16-bit controller based on Infineon's C16x core with embedded teletext and graphic controller functions. M2 can be used for a wide range of TV and OSD applications. This document provides complete reference information on the hardware of M2. Organization of this Document This Users Manual is divided into 14 chapters. It is organized as follows: * Chapter 1, Overview Gives a general description of the product and lists the key features. * Chapter 2, Pin Description Lists pin locations with associated signals, categorizes signals according to function, and describes signals. * Chapter 3, Architectural Overview Gives an overview on the hardware architecture and explains the dataflow within M2. * Chapter 4, C16X Microcontroller Gives a detailed explanation of the 16-bit C architecture. * Chapter 5, Interrupt and Trap Functions, Explains the powerful C166 Interrupt facilities. * Chapter 6, System Control & Configuration Describes how to configure and control the complete C system and the Power Management Unit. * Chapter 7, Peripherals Describes the peripherals (serial buses and timers modules) of the micro. * Chapter 8 & 9, Clock System & Sync System Describes how clocks & syncs for the display generator are generated. * Chapter 10 & 11, Display Generator and D/A Converter Explains the architecture and programming possibilities of the unit which generates the RGB signals. * Chapter 12, Acquisition and Slicer Describes features and functionality of the data caption unit. * Chapter 13, Register Overview Summarizes all HW-registers of M2. * Chapter 14, Electrical Characteristics Lists all important AC and DC values and the maximum operating conditions of M2. Users Manual 1-1 2000-06-15 SDA 6000 Related Documentation For easier understanding of this specification it is recommended to read the documentation listed in the following table. Moreover it gives an overview of the software drivers which are available for M2. Document Name Appl. Note "Initialization and Bootstraploader of M2" Document Purpose System integration support Users Manual 1-2 2000-06-15 SDA 6000 Overview 1 Overview M2 is designed to provide absolute top performance for a wide spectrum of teletext and graphic applications in standard and high end TV-sets and VCRs. M2 contains a data caption unit, a display unit and a high performance Infineon C16x based microcontroller (so that M2 becomes a one chip TV-controller) an up to level 3.5 teletext decoder and display processor with enhanced graphic accelerator capabilities. It is not only optimized for teletext usage but also, due to its extremely efficient architecture, can be used as a universal graphic engine. M2 is able to support a wide range of standards like PAL, NTSC or applications like Teletext, VPS, WSS, Chinatext, Closed Caption and EPG (Electronic Program Guide). With the support of a huge number of variable character sets and graphic capabilities a wide range of OSD applications are also open for M2. A new flexible data caption system enables M2 to slice most data, making the IC an universal data decoder. The digital slicer concept contains measurement circuitries that help identify bad signal conditions and therefore support the automatic compensation of the most common signal disturbances. M2's enhanced data caption control logic allows individual programming, which means that every line can carry an individual service to be sliced and stored in the memory. The display generation of M2 is based on frame buffer technology. A frame buffer concept displays information which is individually stored for each pixel, allowing greater flexibility with screen menus. Proportional fonts, asian characters and even HTML browsers are just some examples of applications that can now be supported. Thus, with the M2, the process of generation and display of on-screen graphics is split up into two independent tasks. The generation of the image in the frame buffer is supported by a hardware graphics accelerator which frees the CPU from power intensive address calculations. The graphics accelerator `prints' the characters, at the desired `screen' position, into the frame buffer memory based on a display list provided by the software. The second part of the display generator (the screen refresh unit) then reads the frame buffer according to the programmed display mode and screen refresh rate and converts the pixel information into an analog RGB signal. Furthermore, M2 has implemented an RGB-DAC for a maximum color resolution of state-of-the-art up to 65536 colors, so that the complete graphic functionality is implemented as a system on chip. The screen resolution is programmable up to SVGA, to cover today's and tomorrow's applications, only limited by the available memory (64 Mbit) and the maximum pixel clock frequency (50 MHz). The memory architecture is based on the concept of a unified memory - placing program code, variables, application data, bitmaps and data captured from the analog TV signal's vertical blanking interval (VBI) in the same physical memory. M2's external bus interface Users Manual 1-3 2000-06-15 SDA 6000 Overview supports SDRAMs as well as ROMs or FLASH ROMs. The organization of the memory is linear, so that it is easy to program the chip for graphic purposes. The SW development environment "MATE" is available to simplify and speed up the development of the software and displayed information. MATE stands for: M2 Advanced Tool Environment. Using MATE, two primary goals are achieved: shorter Time-toMarket and improved SW qualitiy. In detail: * * * * * * * Re-usability Target independent development Verification and validation before targeting General test concept Documentation Graphical interface design for non-programmers Modular and open tool chain, configurable by customer MATE uses available Infineon C166 microcontroller family standard tools as well as a dedicated M2 tools. Users Manual 1-4 2000-06-15 SDA 6000 Overview SIE-MATE Tool Concept: Fast Prototyping on the PC New Tool Generation User Interface Object Editor User Interface Simulator Events and Action Editor Converter Display data info M2 formatted data, Object Library Manager Dedicated M2 Libraries C Compiler C Code Generator Object Code C166-Available C Sources RTOS Linker/Locator Debugging Embedded System M2 PC Simulator + EVA Board M2 - the 16 Bit MC, TTX/EPG/TeleWeb, High End OSD Engine UEB11114 Figure 1-1 M2 Tool Flow Users Manual 1-5 2000-06-15 SDA 6000 Overview Standard Tool Chain For the M2 software development (documentation, coding, debugging and test) the Infineon C166 microcontroller family standard tools can be used: These are ASCII editor, structogram editor, compiler, assembler, linker. Debugging is supported by low-priced ROM-Monitor debuggers or the OCDS (On Chip Debug Support) debugger. M2 Dedicated Tools Special tools are primarily available for platform independent M2 software development and secondly to generate data and control code for the M2 graphical user interface (GDI) without having knowledge of M2 hardware. These are: Display Generator Simulator Teletext Data Slicer Simulator GDI (Graphical Device Interface) Teletext Decoder and Display Software for Level 1.5 and Level 2.5 Mate Display Builder for management, editing, handling and generation of all necessary data to display OSD's * Evaluation Board Simulator to connect a C166 EVA Board to the M2 simulation The M2 software is written in ANSI-C to fulfil the platform independent development. The ported software is code and runtime optimized. The layers of the modular architecture are separated by application program interfaces which ensure independent handling of the modules. * * * * * Users Manual 1-6 2000-06-15 Teletext Decoder with Embedded 16-bit Controller M2 SDA 6000 Version 2.0 CMOS 1.1 General Features * Level 1.5, 2.5, 3.5 WST Display Compatible * Fast External Bus Interface for SDRAM (Up to 8 MByte) and ROM or Flash-ROM (Up to 4 MByte) P-MQFP-128-2 * Embedded General Purpose 16 Bit CPU (Also used as TV-System Controller, C16x Compatible) * Display Generation Based on Pixel Memory * Program Code also Executable From External SDRAM * Embedded Refresh Controller for External SDRAM * Enhanced Programmable Low Power Modes * Single 6 MHz Crystal Oscillator * Multinorm H/V-Display Synchronization in Master or Slave Mode * Free Programmable Pixel Clock from 10 MHz to 50 MHz * Pixel Clock Independent from CPU Clock * 3 x 6 Bits RGB-DACs On-Chip * Supply Voltage 2.5 and 3.3 V * P-MQFP-128 Package Microcontroller Features * * * * * * 16-bit C166-CPU Kernel (C16x Compatible) 60 ns Instruction Cycle Time 2 KBytes Dual Ported IRAM 2 KBytes XRAM On-chip General Purpose Timer Units (GPT1 and GPT2). Asynchronous/Synchronous Serial Interface (ASC0) with IrDA Support. Full-duplex Asynchronous Up To 2 MBaud or Half-duplex Synchronous up to 4.1 MBaud. Type SDA 6000 Users Manual Package P-MQFP-128-2 1-7 2000-06-15 SDA 6000 Overview * High-speed Synchronous Serial Interface (SSC). Full- and Half-duplex synchronous up to 16.5 Mbaud * 3 Independent, HW-supported Multi Master/Slave I2C Channels at 400 Kbit/s * 16-Bit Watchdog Timer (WDT) * Real Time Clock (RTC) * On Chip Debug Support (OCDS) * 4-Channel 8-bit A/D Converter * 42 Multiple Purpose Ports * 8 External Interrupts * 33 Interrupt Nodes Display Features * * * * * * * * * * * * * * * OSD size from 0 to 2046 (0 to 1023) pixels in horizontal (vertical) direction Frame Buffer Based Display 2 HW Display Layers Support of Double Page Level 2.5 TTX in 100 Hz Systems Support of Transparency for both Layers Pixel by Pixel User Programmable Pixel Frequency from 10.0 MHz to 50 MHz Up to 65536 Displayable Colors in one Frame DMA Functionality Graphic Accelerator Functions (Draw Lines, Draw and Fill Rectangle, etc.) 1, 2, 4 or 8-bit Bitmaps (up to 256 out of 4096 colors) 12 bit/16 bit RGB Mode for Display of up to 65535 Colors HW-support for Proportional Characters HW-support for Italic Characters User Definable Character Fonts Fast Blanking and Contrast Reduction Output Acquisition Features * * * * * * * * * * * Two Independent Data Slicers (One Multistandard Slicer + one WSS-only Slicer) Parallel Multi-norm Slicing (TTX, VPS, WSS, CC, G+) Four Different Framing Codes Available Data Caption only Limited by available Memory Programmable VBI-buffer Full Channel Data Slicing Supported Fully Digital Signal Processing Noise Measurement and Controlled Noise Compensation Attenuation Measurement and Compensation Group Delay Measurement and Compensation Exact Decoding of Echo Disturbed Signals Users Manual 1-8 2000-06-15 SDA 6000 Overview 1.2 Logic Symbol VSS VDD(3.3 V) Address 16 Bit XTAL1 XTAL2 RSTIN CVBS1A CVBS1B CVBS2 R G B COR BLANK HSYNC VSYNC RD WR CSROM CSSDRAM MEMCLK UDQM LDQM CLKEN M2 Data 16 Bit Port 2 8 Bit Port 3 15 Bit Port 4 6 Bit Port 5 6 Bit Port 6 7 Bit JTAG 4 Bit VSS VDD(2.5 V) UEL11115 Figure 1-2 Logic Symbol Users Manual 1-9 2000-06-15 Pin Description SDA 6000 Pin Descriptions 2 2.1 Pin Descriptions Pin Diagram (top view) P-MQFP-128-2 VDD25-2 VSS25-2 VDD33-7 VSS33-7 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 RSTIN D11 D3 D4 VDD33-6 VSS33-6 P6.1 P6.0 P5.15 P5.14 P3.15 P3.13 P3.12 P3.11 P3.10 P6.2 P6.3 P6.4 P6.5 P6.6 VSYNC HSYNC COR/RSTOUT BLANK/CORBLA VDD33-8 VSS33-8 XTAL1 XTAL2 VSSA-1 VDDA-1 R G B VSSA-2 VDDA-2 CVBS2 VSSA-3 VDDA-3 CVBS1B CVBS1A VSSA-4 VDDA-4 P5.0 P5.1 P5.2 P5.3 TMODE 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D10 D12 D2 D5 D9 D13 VDD33-5 VSS33-5 D1 D6 D8 D14 D0 D7 VDD33-4 VSS33-4 D15 WR LDQM UDQM RD CSROM CLKEN CSSDRAM MEMCLK P-MQFP-128-2 M2 VDD33-3 VSS33-3 A15/CAS A14/RAS A13 A0 A1 A2 A3 A4 TCK TMS TDI TDO P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 VSS33-1 VDD33-1 VSS25-1 VDD25-1 P4.5/CS3 P4.4/A20 P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 A8 A7 A9 A6 A5 A10 A11 A12 VSS33-2 VDD33-2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 UEP11116 Figure 2-1 Pin Configuration Users Manual 2-3 2000-06-15 SDA 6000 Pin Descriptions 2.2 Table 2-1 Pin No. 37 36 35 34 33 27 26 24 23 25 28 29 30 38 39 40 55 59 65 71 70 64 58 54 57 63 Pin Definitions and Functions Pin Definition and Functions Second Function R0/C0 R1/C1 R2/C2 R3/C3 R4/C4 R5/C5 R6/C6 R7/C7 R8 R9 R10 R11 R12 R13 RAS CAS - - - - - - - - - - Dir. O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Address bit (All addresses are word addresses)/SDRAM Address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/SDRAM address bit Address bit/ Row address strobe for SDRAM access Address bit/ Column address strobe for SDRAM access Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit Data bit 2-4 2000-06-15 Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 Users Manual SDA 6000 Pin Descriptions Table 2-1 Pin No. 67 72 66 62 56 51 47 Pin Definition and Functions (cont'd) Second Function - - - - - - - Dir. I/O I/O I/O I/O I/O I/O O Function Data bit Data bit Data bit Data bit Data bit Data bit External memory read strobe for ROM. RD is activated for every external instruction or data read access. Chip select signal for ROM device Chip select signal for SDRAM device Clock for SDRAM Enable for memory clock Memory write strobe General purpose output port/Address bit General purpose output port/Address bit General purpose output port/Address bit General purpose output port/Address bit General purpose output port/Address bit General purpose output port/Chip select signal for second external static memory Write disable for low byte Write disable for high byte Output of the oscillator amplifier circuit Input of the oscillator amplifier circuit Reset input pin CVBS signal inputs for full service data slicing Ground for CVBS1A (differential input) CVBS signal inputs for WSS data slicing Analog output for red channel Pin Name D10 D11 D12 D13 D14 D15 RD 46 44 43 45 50 22 19 18 17 16 15 49 48 109 108 73 121 120 117 112 CSROM MEMCLK CLKEN WR P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 LDQM UDQM XTAL2 XTAL1 RSTIN CVBS1A CVBS1B CVBS2 R - - - - A16 A17 A18 A19 A20 CS3 - - - - - - - - - O O O O O O O O O O O O O O I I I I I O CSSDRAM - Users Manual 2-5 2000-06-15 SDA 6000 Pin Descriptions Table 2-1 Pin No. 113 114 104 105 103 102 5 6 7 8 9 10 11 12 74 75 76 77 78 79 80 81 82 Pin Definition and Functions (cont'd) Second Function - - RSTOUT CORBLA - VCS EX0IN EX1IN EX2IN EX3IN EX4IN EX5IN EX6IN EX7IN SCL0 SDA0 CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST Dir. O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Analog output for green channel Analog output for blue channel Output for contrast reduction/Reset output Fast blanking signal/Three-level signal for contrast reduction + fast blanking Horizontal sync In/output Vertical sync In/output/Composite sync output General purpose I/O port/External interrupt 0 General purpose I/O port/External interrupt 1 General purpose I/O port/External interrupt 2 General purpose I/O port/External interrupt 3 General purpose I/O port/External interrupt 4 General purpose I/O port/External interrupt 5 General purpose I/O port/External interrupt 6 General purpose I/O port/External interrupt 7 General purpose I/O port/I2C Bus clock line 0 General purpose I/O port/I2C Bus data line 0 General purpose I/O port/GPT2 register CAPREL General purpose I/O port/GPT1 timer T3 toggle General purpose I/O port/GPT1 timer T3 ext. up/down General purpose I/O port/GPT1 timer T4 input for count/gate/reload/capture General purpose I/O port/GPT1 timer T3 count/gate input General purpose I/O port/GPT1 timer T2 input for count/gate/reload/capture General purpose I/O port/SSC masterreceiver/slave-transmit I/O Pin Name G B COR BLANK HSYNC VSYNC P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 Users Manual 2-6 2000-06-15 SDA 6000 Pin Descriptions Table 2-1 Pin No. 83 88 89 90 91 92 124 125 126 127 93 94 95 96 97 98 99 100 101 1 3 Pin Definition and Functions (cont'd) Second Function MTSR TxD0 RxD0 - SCLK - AN.0 AN.1 AN.2 AN.3 T4EUD T2EUD TRIG_IN Dir. I/O I/O I/O I/O I/O I/O I I I I I/O I/O I/O Function General purpose I/O port/SSC mastertransmit/slave-receiver O/I General purpose I/O port/ASC0 clock/data output General purpose I/O port/ASC0 data input (asynchronous) or I/O (synchronous.) General purpose I/O port General purpose I/O port/SSC master clock output/slave clock input General purpose I/O port General purpose I/O port/Analog input for A/D-converter General purpose I/O port/Analog input for A/D-converter General purpose I/O port/Analog input for A/D-converter General purpose I/O port/Analog input for A/D-converter General purpose I/O port/GPT1 timer T4 ext.up/down ctrl. input General purpose I/O port/GPT1 timer T2 ext.up/down ctrl. input General purpose I/O port/Trigger input-signal for `On Chip Debug System' (OCDS) General purpose I/O port/Trigger outputsignal for `On Chip Debug System' (OCDS) General purpose I/O port General purpose I/O port/I2C bus clock line 1 General purpose I/O port/I2C bus data line 1 General purpose I/O port General purpose I/O port/I2C bus data line 2 Clock for JTAG interface Data input for JTAG interface 2-7 2000-06-15 Pin Name P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 P5.0 P5.1 P5.2 P5.3 P5.14 P5.15 P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 TCK TDI TRIG_OUT I/O - SCL1 SDA1 - SDA2 - - I/O I/O I/O I/O I/O I I Users Manual SDA 6000 Pin Descriptions Table 2-1 Pin No. 4 2 128 110 111 115, 118, 122 116, 119, 123 Pin Definition and Functions (cont'd) Second Function - - - - - - Dir. O I I S S S Function Data output for JTAG interface Control signal for JTAG interface Testmode pin1) Analog ground Analog power (for PLL and DAC) (2.5 V) Analog ground Pin Name TDO TMS TMODE VSSA-1 VDDA-1 VSSA2-4 VDDA2-4 - S Analog power (for ADCs) (2.5 V) 20, 86 VSS25 1-2 21, 87 VDD25 1-2 13, 31, VSS33 1-8 41, 52, 60, 68, 84, 107 14, 32, VDD33 1-8 42, 53, 61, 69, 85, 106 1) - - - S S S Digital ground (for digital core) Digital power (for digital core) (2.5 V) Digital ground for pads - S Digital power (for pads) (3.3 V) (Must be kept to "0" in application.) Users Manual 2-8 2000-06-15 Architectural Overview 3 CVBS1 Data Internal RAM 2 Kbyte 16 Slicer1 Figure 3-1 -Cache Boot ROM 16 32 Instr./Data 16...21 16 Addr. External Bus Interface Interrupt Controller PEC 16 36 nodes (8 ext.) X-BUS Instr./Data 16 D-Cache Architectural Overview M2 Top Level Block Diagram CPU-Core C166 Data 16 OSC (6 MHz) XTAL GPT1 T2 T3 T4 GPT2 T5 T6 OCDS 4Channel ADC 7-bit USART ASC SPI SSC Data 16 XRAM 2 Kbyte GA SRU AMI Users Manual C 2 CVBS2 ACQ Slicer2 3-3 RTC Port 5 6 V Port 3 15 Port 2 8 Port 4 8 D-Sync Watchdog JTAG FIFO 3 x 6 Bit DAC Port 6 7 UEB10716 4 3 SDA 6000 Architectural Overview 2000-06-15 H SDA 6000 Architectural Overview The architecture of M2 comprises of a 16-bit microcontroller which is derived from the well known Infineon Technologies C16x controller family. Due to the core philosophy of M2, the architecture of the CPU core is the same as described in other Infineon Technologies C16x derivatives. The CPU, with its peripherals, can be used on one hand to perform all TV controlling tasks, and on the other hand to process the data, sliced by the slicer, and the acquisition unit according to the TTX standard. Furthermore it is used to generate an "instruction list" for the graphic accelerator which supports the CPU by generating the display. M2 has integrated two digital slicers for two independent CVBS signals. One slicer is used to capture the data (e.g. Teletext or EPG) from the main channel, the other slicer can be used to slice the WSS information from a different channel, which is helpful e.g. to support PIP applications in 16:9 TVs. Both slicers separate the data from the analog signal and perform the bit synchronization and framing code selection before the data is stored in a programmable VBI buffer in the external RAM. Capturing and storing the raw data in the RAM does not need any CPU power. M2's display concept has improved in comparison to the common known state of the art Teletext-ICs. The display concept is based on a pixel orientated attribute definition instead of the former character orientated attribute definition. For the processing of this new pixel based attribute definition the display generator architecture is divided in two subblocks: the graphic accelerator (GA) and the screen refresh unit (SRU). The graphic accelerator is used to modify the frame buffer. From an abstract point of view, the graphic accelerator is a DMA which is optimized for OSD functionality, so e.g. bitmaps can be copied to the frame buffer. The graphic accelerator is used to draw rectangles, parallelograms, horizontal, vertical and diagonal lines. The user does not need to access the graphic accelerator directly, thanks to an easy to handle SW-GDI function which is available with the M2 hardware. The DMA functionality of the display generator (DG) supports the pixel transfer between any address of entire external memory. The teletext and graphic capabilities can be used simultaneously, so that M2 can combine teletext information with e.g. background images and advanced high resolution OSD graphics. M2 uses the frame buffer located in external memory so every bitmap can be placed at any location on the screen. The contents of the frame buffer does not have to be set up in real time. The duration of the set up of the screen depends on the contents of the displayed information. M2 supports two hardware display layers. To refresh the screen the M2 reads and mixes two independent pixel sources simultaneously. Different formats of the pixels which are part of different applications (e.g. Teletext formats, 12-bit RGB or 16-bit RGB values) can be stored in the same frame buffer at the same time. Users Manual 3-4 2000-06-15 SDA 6000 Architectural Overview The screen refresh unit is used to read the frame buffer pixel by pixel in real time and to process the transparency and RGB data. A color look up table (CLUT) can be used to get the RGB data of the current pixel. Afterwards the RGB data is transferred to the D/A converter. The blank signal and contrast reduction signal (COR) is also processed for each pixel by the SRU and transferred to the corresponding output pins. The pixel, line and field frequencies are widely programmable so that the sync system can be used from low end 50 Hz to high end 100 HZ TV applications as well as for any other standard. The on chip clock system provides the M2 with its basic clock signals. Independent clock domains are provided for the embedded controller, the bus interface and the display system. The pixel clock can vary between 10 MHz and 50 MHz. Due to the unified memory architecture of M2, a new bus concept is implemented. An arbiter handles the bus requests from the different request sources. These are: * * * * * * Slicer 1 requests (normally used as a TTX slicer) Slicer 2 requests (used as a WSS slicer) Graphic accelerator requests Screen refresh unit requests Data requests from the CPU via XBUS Instruction requests via the CPU program bus For exploiting the full computational power of the controller core the code of time critical routines can be stored in one bank of the external SDRAM separated from all display information (frame buffer, character set etc.). An instruction cache (I-CACHE) is used for buffering instruction words in order to minimize the probability of wait states to occur when the microcontroller is interfering with the display generator (DG) for access rights to the external memory devices. The data cache (D-CACHE) serves for operand reads and writes via the XBUS from/to external memory devices. The external bus interface (EBI) features interleaved access cycles to one or two static external memory devices (ROM, Flash-ROM or SRAM) with a total maximum size of 4 MByte and one PC100 compliant (Intel standard) SDRAM device (16 MBit organized as 2 memory banks or 64 MBit organized as 4 memory banks). For TV controlling tasks M2 provides three serial interfaces (I2C, ASC, SSC), two general purpose timers, (GPT1, GPT2), a real time clock (RTC), a watch dog timer (WDT), an A/D converter and eight external interrupts. Users Manual 3-5 2000-06-15 C16X Microcontroller SDA 6000 C16X Microcontroller 4 4.1 C16X Microcontroller Overview M2's microcontroller and its peripherals are based on a Cell-Based Core (CBC) which is compatible to the well known C166 architecture. In M2, the CPU and its peripherals are generally clocked with 33.33 MHz which results in an instruction cycle time of 60 ns. The implementation of the microcontroller within M2 deviates from other known C16x derivates since the controller's XBUS is not used as the external bus. All external access cycles of the microcontroller, the display generator and the acquisition unit are performed via a high performance time interlocking SDRAM bus. The external bus interface (EBI) manages the arbitration procedure for access cycles to the external synchronous DRAM in parallel to an external static memory (ROM or FLASH; for more details refer to Chapter 4.4). Due to the realtime critical bus bandwidth requirements of the display generator, unpredictable wait-states for the controller may occur. These wait-states do not destroy the overall average system performance, because they are mostly buffered by the CPU related instruction and data buffers. Nevertheless they can influence, for example, the worst disconnection response time. Emulation is now performed by an on-chip debug module which can be accessed by a JTAG interface. The following microcontroller peripherals are implemented: * * * * * * * * * * * * 2 KByte IRAM (System RAM) 2 KByte XRAM (XBUS located) 32 Interrupt Nodes General Purpose Timer Units (GPT1 and GPT2) Real Time Clock (RTC) Asynchronous/Synchronous Serial Interface (ASC0) High-Speed Synchronous Serial Interface (SSC) I2C Bus Interface (I2C) 4-Channel 8-bit A/D Converter (ADC) Watchdog Timer (WDT) On-Chip Debug Support Module (OCDS) 42 Multiple Purpose Ports Central Processing Unit The CPU executes the C166 instruction set (with the extensions of the C167 products). Its main features are the following: * 4-stage pipeline (Fetch, Decode, Execute and Write-Back). * 16 x 16-bit General Purpose Registers * 16-bit Arithmetic and Logic Unit Users Manual 4-3 2000-06-15 SDA 6000 C16X Microcontroller * Barrel shifter * Bit processing capability * Hardware support for multiply and divide instructions Internal RAM (IRAM) The internal dual-port RAM is the physical support for the General Purpose Registers, the system stack and the PEC pointers. Due to its close connections with the CPU, the internal RAM provides fast access to these resources. As the GPR bank can be mapped anywhere in the internal RAM through a base pointer (Context Pointer CP), fast context switching is allowed. The internal RAM is mapped in the memory space of the CPU and can be used also to store user variables or code. Interrupt Controller Up to 32 interrupt sources can be managed by the Interrupt Controller through a multiple priority system which provides the user with the ability to customize the interrupt handling. The interrupt system of M2 includes a Peripheral Event Controller (PEC). This processor performs single-cycle interrupt-driven byte or word transfers between any two locations in the entire memory space of M2. In M2, the PEC functionalities are extended by the External PEC which allows an external device to trigger a PEC transfer while providing the source and destination pointers. New features also include the packet transfer mode and the channel link mode. Besides user interrupts, the Interrupt Controller provides mechanisms to process exceptions or error conditions, so-called "hardware traps", that arise during program execution. System Control Unit M2's System Control Unit (CSCU) is used to control system specific tasks such as reset control or power management within an on-chip system built around the core. The power management features of the CSCU provide effective means to realize standby conditions for the system with an optimum balance between power reduction, peripheral operation and system functionality. The CSCU also provides an interface to the Clock Generation Unit (CGU) and is able to control the operation of the Real Time Clock (RTC). The CSCU includes the following functions: * * * * * * System configuration control Reset sequence control External interrupt and frequency output control Watchdog timer module General XBUS peripherals control Power management additional to the standard Idle and Power Down modes 4-4 2000-06-15 Users Manual SDA 6000 C16X Microcontroller * Control interface for Clock Generation Unit * Identification register block for chip and CSCU identification OCDS The On-Chip Debug System allows the detection of specific events during user program execution through software and hardware breakpoints. An additional communication module allows communication between the OCDS and an external debugger, through a standard JTAG port. This communication is performed in parallel to program execution. 4.2 Memory Organization In normal operation mode the memory space of the CPU is configured in a "Von Neumann" architecture. This means that code and data are accessed within the same memory areas, i. e. external memory, internal controller memory (IRAM), the address areas for integrated XBUS peripherals (I2C, internal XBUS memory (XRAM)) and the special function register areas (SFR, ESFR) are mapped into one common address space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each. All internal memory areas and the address space of the integrated XBUS peripherals are mapped to segment 0. Code and data may be stored in any part of the memory, except for the SFR blocks, which can not be used for instructions. Despite this equivalence of code and data, proper partitioning is necessary to make use of the full bandwidth of the memory system. The integrated C16x controller communicates via 2 busses with the memory interface. In normal operation mode access to segments 00H to 41H (excluding internal memory areas) is mapped to the read only program memory bus (PMBUS), whereas access to segments 42H to FFH is mapped to the XBUS. In bootstrap loader mode (BSLMode) instruction fetches to external memory areas via PMBUS are redirected to the internal bootstrap loader ROM (BSLROM). Operand (data) accesses remain unchanged. The PMBUS is connected to the instruction cache (ICACHE) which operates as readahead FIFO (see Figure 4-1). The data cache (DCACHE) which is connected to the XBUS holds a maximum of 4 words corresponding to one SDRAM burst. Accesses of DCACHE, ICACHE and the acquisition unit (ACQ) are joined within the acquisition memory interface (AMI) and directed to the external bus interface (EBI). Redirections via ESFR REDIR (instruction fetches only) and ESFR REDIR1 are done in the AMI (see Chapter 4.5.1). The EBI joins AMI and display generator (DG) accesses and reads data from or writes data to the external static and dynamic memory devices (see Chapter 4.5 for further information). In case of cache miss wait states are inserted until the data is ready. IRAM, XRAM and the special function register areas can be accessed without wait states. Users Manual 4-5 2000-06-15 SDA 6000 C16X Microcontroller External Memory M2 DG SDRAM Boot ROM PMBUS ROM1 EBI ICACHE C16X XBUS AMI ROM2 DCACHE ACQ UED11214 Figure 4-1 M2 Memory Path Block Diagram All memory locations are byte and word readable. The internal memories (IRAM, XRAM) and the external dynamic memory (SDRAM) are byte and word writable, but external static memory is only word writable. Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations, with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (instructions only) are stored in ascending memory locations as two subsequent words. Single bits are always stored in the specific bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address. Bit addressing is supported by a part of the special function registers, a part of the IRAM and the general purpose registers (GPRs). Users Manual 4-6 2000-06-15 SDA 6000 C16X Microcontroller Figure 4-2 Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. 4.3 On-Chip Microcontroller RAM and SFR Area The IRAM/SFR area is located within data page 3, and provides access to 2 KByte of dual ported IRAM and two 512 Byte blocks of Special Function Registers (SFRs). The internal RAM (IRAM) serves several purposes: * * * * * System Stack (Programmable Size) General Purpose Register Banks (GPRs) Source and Destination Pointers for the Peripheral Event Controller (PEC) Variable and other data storage, or Code storage Users Manual 4-7 2000-06-15 SDA 6000 C16X Microcontroller Segment 0 64 Kbytes RAM / SFR Area 00'FFFF H 00'F000 H 00'E800 H 00'E000 H Page 3 RAM / SFR Area 4 Kbytes 00'FFFF H SFR Area 00'FE00 H 2C XRAM 00'C000 H Page 2 2 Kbyte IRAM 00'8000 H Page 1 00'F600 H 00'FA00 H 00'4000 H Reserved 00'F200 H ESFR Area Page 0 00'0000 H 00'F000 H UED11213 Figure 4-3 Internal RAM Areas and SFR Areas Note: The upper 256 bytes of SFR area, ESFR area and IRAM are bit-addressable (see shaded blocks in Figure 4-3). Code accesses are always made through even byte addresses. The highest possible code storage location in the IRAM is either 00'FDFEH for single word instructions, or 00'FDFCH for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossings from IRAM to the SFR area are not supported and cause erroneous results. Any word and byte data in the IRAM can be accessed via indirect or long 16-bit addressing modes if the selected DPP register points to page 3. Any word data access is made through an even byte address. The highest possible word data storage location in the IRAM is 00'FDFEH. For PEC data transfers, the IRAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. Users Manual 4-8 2000-06-15 SDA 6000 C16X Microcontroller The upper 256 Byte of the IRAM (00'FD00H through 00'FDFFH) and the GPRs of the current bank are provided for single bit storage, and thus they are bit addressable. 4.3.1 System Stack The system stack may be defined within the IRAM. The size of the system stack is controlled by bit field STKSZ in the SYSCON register (see table below). For all system stack operations, the IRAM is accessed via the Stack Pointer (SP) register. The stack grows downward from higher to lower RAM address locations. Only word accesses are supported by the system stack. A stack overflow (STKOV) and a stack underflow (STKUN) register are provided to control the lower and upper limits of the selected stack area. These two stack boundary registers can be used not only for protection against data destruction, but also to implement flushing and filling a circular stack with a hardware supported system stack (except for option `111'). 4.3.2 General Purpose Registers The General Purpose Registers (GPRs) use a block of 16 consecutive words within the IRAM. The Context Pointer (CP) register determines the base address of the currently active register bank. This register bank may consist of up to 16 word GPRs (R0, R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte GPRs are mapped onto the first eight word GPRs (see Table 4-1). In contrast to the system stack, a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short 2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as a base address (independent of the current DPP register contents). In addition, each bit in the currently active register bank can be accessed individually. Users Manual 4-9 2000-06-15 SDA 6000 C16X Microcontroller Table 4-1 Internal RAM Address M2 supports fast register bank (context) switching. Multiple register banks can physically exist within the IRAM at the same time. However, only the register bank selected by the Context Pointer register (CP) is active at a given time. Selecting a new active register bank is simply done by updating the CP register. A particular Switch Context (SCXT) instruction performs register bank switching and automatically saves the previous context. The number of implemented register banks (arbitrary sizes) is only limited by the size of the available internal RAM. 4.3.3 PEC Source and Destination Pointers The 16 word locations in the IRAM from 00'FCE0H to 00'FCFEH (just below the bitaddressable section) are provided as source and destination offset address pointers for data transfers on the eight PEC channels. Each channel uses a pair of pointers stored in two subsequent word locations, with the source pointer (SRCPx) on the lower and the destination pointer (DSTPx) on the higher word address (x = 7 ... 0). In M2, these pointers are used to specify the address offset within the segment, and the destination / source segment numbers are specified in designated SFRs (see Chapter 5.2). Users Manual 4 - 10 2000-06-15 SDA 6000 C16X Microcontroller 00'FD00 H 00'FCFE H 00'FCFC H DSTP7 SRCP7 PEC Source and Destination Pointers 00'FCE2 H 00'FCE0 H DSTP0 SRCP0 00'FCFE H 00'FCE0 H 00'FDDE H Internal RAM 00'F600 H 00'F5FE H MCD02266 Figure 4-4 Location of the PEC Pointers Whenever a PEC data transfer is performed, the pair of source and destination pointers, which is selected by the specified PEC channel number, is accessed independent of the current DPP register contents; the locations referred to by these pointers are also accessed independent of the current DPP register contents. If a PEC channel is not used, the corresponding pointer locations are available and can be used for word or byte data storage. 4.3.4 Special Function Registers The so-called Special Function Registers (SFRs) are provided to control internal functions of M2 (CPU, bus interface, Interrupt Controller, OCDS) or peripherals connected to the Peripheral Bus. These SFRs are arranged within two areas of 512 Bytes each. The first register block, the SFR area, is located in the 512 Bytes above the internal RAM (00'FFFFH ... 00'FE00H); the second register block, the Extended SFR (ESFR) area, is located in the 512 Bytes below the IRAM (00'F1FFH ... 00'F000H). Special function registers can be addressed via indirect and long 16-bit addressing modes. Using an 8-bit offset together with an implicit base address allows word SFRs and their respective low bytes to be addressed. However, this does not work for the respective high bytes! Users Manual 4 - 11 2000-06-15 SDA 6000 C16X Microcontroller Note: Writing to any byte of an SFR causes the non-addressed complementary byte to be cleared! The upper half of each register block is bit-addressable, so the respective control/status bits can directly be modified or checked using bit addressing. When accessing registers in the ESFR area using 8-bit addresses or direct bit addressing, an Extend Register (EXTR) instruction is first required to switch the short addressing mechanism from the standard SFR area to the Extended SFR area. This is not required for 16-bit and indirect addresses. The GPRs R15 ... R0 are duplicated, i.e. they are accessible within both register blocks via short 2-, 4- or 8-bit addresses without switching. ESFR_SWITCH_EXAMPLE: EXTR #4 MOV ODP2, #data16 BFLDL DP6, #mask, #data8 BSET DP1H.7 MOV T8REL, R1 ;Switch to ESFR area for next 4 instr. ;ODP2 uses 8-bit reg addressing ;Bit addressing for bit fields ;Bit addressing for single bits ;T8REL uses 16-bit mem address, ;R1 is duplicated into the ESFR space ;(EXTR is not required for this access) ;The scope of the EXTR #4 instruction... ; ... ends here! ;T8REL uses 16-bit mem address, ;R1 is accessed via the SFR space ;---- ;------------------- MOV T8REL, R1 In order to minimize the use of the EXTR instructions the ESFR area primarily holds registers which are required mainly for initialization and mode selection. Registers that need to be accessed frequently are allocated, wherever possible, to the standard SFR area. Note: The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions. 4.4 External Memory M2 provides an external bus interface (EBI) to access an external SDRAM, together with an external static memory device (ROM or SRAM). To optimize the overall system performance, access to both memory types is interlocked. Because of high performance requirements M2 provides only one bus type (Demultiplexed 16-bit Bus). Depending on the reset configuration (refer to Chapter 6.1) an external ROM/SRAM size from 128 KByte up to 4 MByte can be chosen. Although external addresses (represented by pins A0 ... A20) are always word addresses, byte accesses to the SDRAM are possible by using mask signals LDQM and UDQM. Users Manual 4 - 12 2000-06-15 SDA 6000 C16X Microcontroller 4.4.1 SDRAM PC SDRAM compliant (Intel standard) memory devices with 2 or 8 MByte and a minimum clock period of 10 ns (latency 3) may be connected to M2's external memory bus. Supported data organizations are given below: Memory Size 2 MByte 8 MByte # SDRAM Banks 2 4 # Bank Addresses 1 2 # Row Addresses 11 12 # Column Addresses 8 8 The external SDRAM connected to M2 is a multifunctional, byte or word addressable device which can be used for frame buffers, character sets, pixel graphics, acquisitions, microcontroller workspace and any other data storage purposes. Using a 100 MHz external memory bus the theoretical optimum memory bandwidth is limited to 200 MByte/s. In order to keep the sustainable memory bandwidth as close to the optimum as possible, the bank oriented architecture of SDRAM devices has to be exploited. Basically, display related information should be separated from controller related data items. The following allocation is recommended for a 2 bank, 2 MByte device: * "Display Bank": Both Frame Buffers, Character Set, Pixel Graphic, Graphic Accelerator Instructions (GAI), Application Data (i.e. TTX, EPG, ...) * "Controller Bank": Instruction Code, VBI-buffer, Application Data (i.e. TTX, EPG, ...) The suggested allocation leads to best performance results since it reduces the number of time consuming row commands on the SDRAM. 4.4.2 External Static Memory Devices M2 supports access to external ROM, Flash ROM and SRAM devices which provide a read cycle time tRC < 120 ns. Only 16-bit word access is supported. The maximum memory size is limited by the number of external address lines. Up to 21 external address lines are configurable, thus devices providing up to 4 MByte of static external memory can be connected to M2. 4.5 External Bus Interface (EBI). The EBI handles access channels to four SDRAM banks within one SDRAM device and up to two static memory devices at 100 MHz. (For lower requirements the clock frequency can be reduced to 66 MHz, refer to Chapter 8). A maximum of three external memory devices is supported. Figure 4-5 shows the possible configurations. Users Manual 4 - 13 2000-06-15 SDA 6000 C16X Microcontroller 2...8 MByte SDRAM (2...4 banks) ROM or Flash-ROM 128 KByte...4 MByte ROM or Flash-ROM 128 KByte...4 MByte M2 UEB11118 Figure 4-5 External Memory Configuration The interlocking execution of access cycles to different memory modules is supported. All external SDRAM access cycles must be executed with a pre-defined burst length BL = 4 and latency 3. Write access cycles, which modify less than four SDRAM locations, are achieved by activating mask control signals L/UDQM. The integrated refresh controller of the EBI checks for the compliance of refresh periods and executes refresh operations on the SDRAM devices. The configuration of different external SDRAM types can be controlled by a special SW driver as well as refresh modes and power down features. The microcontroller and the acquisition unit use a common interface to the EBI. A separate connection to the EBI is provided for the display generator. The EBI performs an arbitration procedure for granting right access to either of the request sources. But granting right access to one source does not exclude requests initiated by the other source from being served. A maximum of two access requests from a source may be served consecutively if the other source is addressing an SDRAM location. Up to four consecutive access cycles from the same source are served if the other source is addressing an external ROM device. The following figures show typical timing diagrams that may be observed on the external bus. The first figure presents the interlocked execution of access cycles to the external ROM and a SDRAM device. The other figure resumes the situation when both sources address locations are in different SDRAM banks. Detailed timings and the specification of setup and hold conditions can be found in Chapter 14. Users Manual 4 - 14 2000-06-15 SDA 6000 C16X Microcontroller MEMCLK CSSDRAM Act RAS Read CAS Write WR A(21:0) ca SDRAM Data ROM_Adr ROM Data ra ra D(15:0) CSROM RD UET11119 Figure 4-6 Interlocked Access Cycles to ROM and SDRAM Users Manual 4 - 15 2000-06-15 SDA 6000 C16X Microcontroller MEMCLK Pre RAS Read CAS SDRAM: 16 MBit, 2 Banks A (9:0) ra ca ca ra ca ra Read Read Read Act Act Pre Act A10 Bank 1 A11 b1 ra ra Bank 0 ra b1 b1 b1 b0 b0 b1 b1 SDRAM: 64 MBit, 4 Banks A (9:0) ra ca ca ra ca ra A10 ra ra ra A11 Bank Y A(13:12) by Precharge ra ra Bank X ra by Activate dx by by bx Activate bx by Precharge by Activate dx dy 2 3 4 1 2 3 4 dy 5 6 7 8 D(15:0) 6 7 8 1 1 zo UET11120 Figure 4-7 Interlocked Access Cycles to two SDRAM Banks 4.5.1 Memory Mapping Mapping of memory locations from the address space of the C16x to physical addresses (and chip selects) occurs in 4 steps (all addresses shown below are byte addresses unless otherwise noted). Figure 4-8 gives a coarse depiction (without redirection) of the mapping process in normal operation mode. Users Manual 4 - 16 2000-06-15 SDA 6000 C16X Microcontroller EBI Address-Space FF'FFFF H C16X Address-Space EBI Address-Space FF'FFFF H D XBUS 80'0000 H S2 60'0000 H S1 40'0000 H A 41'0000 H 41'0000 H PMBUS 01'8000 H 00'8000 H 00'0000 H B D 80'0000 H S2 41'0000 H 40'0000 H C S1 00'0000 H UED11212 Figure 4-8 Memory Mapping from C16x address-space to EBI address-space for 1 64MBit SDRAM (D) and 2 16MBit static memory devices (S1, S2) is shown on the left (XBUS/ PMBUS overlap). The right part shows the mapping for 1 64MBit SDRAM (D) and 2 32MBit static memory devices (S1, S2) (no XBUS/PMBUS overlap). Redirection via REDIR/REDIR1 is not shown. The exclusion of the address space for internal memories B leads to 1 segment in physical memory that is either addressable only via PMBUS A or not addressable at all C. To get access to these segments use REDIR1. a) Internal mapping of the C16x: Access to segments 0 to 64 selects the PMBUS. The address range (00'0000H ... 40'FFFFH) is mapped to the range 00'0000H ... 3F'FFFFH shown to the ICACHE, thus omitting the internal memories, the special function register areas and the XBUS peripheral address space contained the range 00'8000H ... 01'7FFFH: * C16x addresses * C16x addresses 00'0000H ... 00'7FFFH are mapped to 00'0000H ... 00'7FFFH 01'8000H ... 40'FFFFH are mapped to 00'8000H ... 3F'FFFFH Users Manual 4 - 17 2000-06-15 SDA 6000 C16X Microcontroller Access to segments 65 to 255 selects the XBUS. This address range (41'0000H ... FF'FFFFH) is not remapped by the C16x. b) Mapping by caches: In normal operation mode the address requested by the controller is not altered by ICACHE and DCACHE. In bootstrap loader mode, instruction fetches via the ICACHE are mapped to the boot ROM by the ICACHE: * Address is mapped to address mod 40H Operand reads via ICACHE and all accesses via DCACHE are passed unaltered to the AMI. c) Mapping and redirection in AMI: Address mapping in AMIdepends on the settings of the ESFRs REDIR and REDIR1 as well as on the total amount of static memory. The mapping is done in the following order: 1) Check for redirection via REDIR1: If the requested address lies in segment 255 the segment address is replaced by the low byte of REDIR1. 2) Check for redirection via REDIR: If the address resulting from step1 lies in the address range specified by REDIR, the address is shifted to SDRAM area: * Address is mapped to 80'0000H + address - REDIR_LOWER x 16 kBytes 3) If the total amount of static memeory in 4 MBytes or less (i.e. SALSEL "111" or SALSEL = "111" and no second device present) and the address resulting from step 2 is below 4 MBytes the address is shifted by 4 MBytes: * Address is mapped to address + 40'0000H This means that the address ranges 02'0000H ... 40'FFFFH (PMBUS) and 41'0000H ... 7F'FFFFH (XBUS) in the address space of the C16x are mapped to the same physical memory. The overlap allows to make use of 2 independent busses for code (PMBUS) and data (XBUS) for fast parallel access. If the total amount of static memory is 8 MBytes (i.e. SALSEL = "111" and a second device is present) no further mapping occurs. d) Mapping to addresses of specific physical devices by EBI: 1) dynamic memory: * addresses 80'0000H ... FF'FFFFH (9F'FFFFH) access the 64MBit (16 MBit) SDRAM (CSSDRAM) 2) static memory: In the total amount of static memory is 4 MBytes or less (see above) the requests of the AMI or the DG in the address range 40'0000H ... 7F'FFFFH are passed to the external static memory devices according to the SALSEL and CSENA settings (see Chapter 6.1). The address range 00'0000H ... 3F'FFFFH must not be used. If the total amount of the static memory is 8 MBytes there is no reserved address range: Users Manual 4 - 18 2000-06-15 SDA 6000 C16X Microcontroller * Addresses 00'0000H ... 3F'FFFFH access the first static memory device (CSROM) * Addresses 40'0000H ... 7F'FFFFH access the second static memory device (CS3) The addresses shown on the external address lines of M2 are word oriented, starting at 0 for each device. The External Bus Interface (EBI) provides a special mode, the "EBI direct mode", where the control pins to the SDRAM device are directly controlled by the CPU while the HW finite state machines of the EBI are bypassed. "EBI direct mode" is used for accomplishing operations on the SDRAM such as the execution of the requisite initialization sequence, power down mode entry/exit etc. When executing a direct mode command the EBI shifts the contents of register EBIDIR into the SDRAM control lines. The INFINEON SDRAM driver (refer to document list) provides appropriate functions for executing operations in direct mode. 4.5.2 Register Description Access cycles to addresses specified by bit fields REDIR_LOWER and REDIR_UPPER are redirected by hardware to the SDRAM area. The area to which the specified range is mapped, starts at the base address (80'0000H) of the SDRAM. The range for redirection is selected in groups of 16 KByte. Using the REDIR register, access cycles to ROM located routines may be redirected to copies of these routines in the SDRAM. REDIR 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 REDIR_UPPER (7:0) REDIR_LOWER (7:0) rw Bit Function rw REDIR_LOWER Base address of selected range in the ROM Area (7:0) Bitfield REDIR_LOWER specifies the MSBs of the base address of the selected range. REDIR_UPPER (7:0) Upper address of selected range in the ROM Area (exclusive) Bitfield REDIR_UPPER specifies the MSBs of the first no longer redirected 16 KBytes. To gain access to memory areas covered by the read only PMBUS or to areas not accessible at all (see Figure 4-8) accesses to segment 255 can be redirected to any other segment in EBI address space. Users Manual 4 - 19 2000-06-15 SDA 6000 C16X Microcontroller REDIR1 15 14 13 12 - Reset Value: 00FFH 11 10 9 8 7 6 5 4 3 2 1 0 REDIR1_SEG (7:0) rw Bit REDIR1_SEG (7:0) Function For access to segment 255, the segment part of the address is replaced by REDIR1_SEG. The configuration of the "External Bus Interface" and its operation mode is defined with the EBICON register. EBICON 15 - Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 REF EN 2 SDR SZE 1 ED MA 0 ED MR rw Bit EDMR Function EBI Direct Mode Request Flag `0': EBI direct mode is disabled `1': EBI direct mode is enabled r r rw Note: This bit is only used for EBI direct mode. EDMA EBI Direct Mode Acknowledge Flag `0': The EBI has not (yet) entered direct mode `1': The EBI has entered direct mode Note: This bit is only used for EBI direct mode. SDRSZE SDRAM Size `0': 16 MBit (2 x 2048 x 256 x 2B), 2 banks (bank = adr_11) `1': 64 MBit (4 x 4096 x 256 x 2B), 4 banks (bank = adr_13:12) Refresh Controller Enable Bit `0': Refresh controller for SDRAM is disabled `1': Refresh controller for SDRAM is enabled REFEN The EDMR request flag and the hardware controlled acknowledge flag EDMA are used during "EBI direct mode" for implementing a four-phase handshake which guarantees that each direct mode command is executed exactly once by the EBI. Users Manual 4 - 20 2000-06-15 SDA 6000 C16X Microcontroller Phase EDMR I II III IV EDMA UET11123 Figure 4-9 Four-Phase Handshake * Phase I: The controller requests a direct mode command which has not yet been executed by the EBI. The controller must not reset the EDMR bit until the EBI acknowledges the EDMA bit (EDMA polling required). * Phase II: The EBI acknowledges the EDMA bit after executing the requested direct mode command. The EBI will not reset the EDMA bit before the requested EDMR bit is reset. * Phase III: The requested EDMR bit is reset while the acknowledged EDMA bit is still valid. This phase will only take one EBI clock period (no EDMA polling required). * Phase IV: EBI is waiting for the next direct mode request. When executing a direct mode command the EBI shifts the contents of register EBIDIR into the external control pins of the SDRAM. EBIDIR 15 - Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 CLK EN 4 CS _N 3 RAS _N 2 CAS _N 1 WR _N 0 ADR _10 rw Bit ADR_10 WR_N CAS_N RAS_N CS_N CLKEN Function rw rw rw rw rw Control Bit for Address Pin A10 in Direct Mode Control Bit for Pin WR in Direct Mode Control Bit for Pin CAS (A15) in Direct Mode Control Bit for Pin RAS (A14) in Direct Mode Control Bit for Pin CSSDRAM in Direct Mode Control Bit for Pin CLKEN in Direct Mode Users Manual 4 - 21 2000-06-15 SDA 6000 C16X Microcontroller The setting required for initiating a certain command on the SDRAM has to be written to the EBIDIR register before the direct mode request, the EDMR bit in the EBICON register is asserted. The following table shows the commands that may be executed in direct mode along with the associated settings of the EBIDIR register. CLKEN CLKEN CS_N RAS_N CAS_N WE_N ADR_10 n-1 n Device deselect DSEL No Operation NOP Precharge all banks PALL Auto refresh CBR Self refresh entry SELFRSH Self refresh exit SELFRSHX Power down entry PWRDN Power down exit PWRDNX Mode register set MRS 1) 1 1 1 1 1 0 1 0 1 dc1) dc dc 1 0 1 0 1 dc 1 0 0 0 0 1 dc 1 0 dc 1 0 0 0 dc dc dc 0 dc 1 1 0 0 dc dc dc 0 dc 1 0 1 1 dc dc dc 0 dc dc 1 dc dc dc dc dc 0 dc = don't care The MRS command (mode register set) is used to program the SDRAM for the desired operating mode. When executing the MRS command, address lines A11-A10 encode the operating mode. M2 then issues a hardwired pattern that sets the SDRAM to latency mode 3, wrap type linear and burst length 4. For the correct handling of access cycles the user has to provide the EBI with information about the external memory configuration and memory sizes. The combination of reset configuration and the SDRSZE bit of the EBICON register includes all the information needed. Based on these inputs the EBI constructs its internal address map for allocating ROM devices and SDRAM banks. The external memory configuration is defined with bit CSENA of the RP0H register (refer to Chapter 6.1). The memory configuration controls the correct behavior of pin CS3. Users Manual 4 - 22 2000-06-15 SDA 6000 C16X Microcontroller . Bit CSENA Function Chip Select Enable `0': CS3 is active for 2nd ROM device `1': CS3 is inactive The allocation of address ranges for the SDRAM banks is controlled through the SDRSZE bit. SDRSZE = `0' (16 MBit): Address Ranges of Banks Bank Bank1 Bank2 Address Range 80'0000H - 8F'FFFFH 90'0000H - 9F'FFFFH SDRSZE = `1' (64 MBit): Address Ranges of Banks Bank Bank1 Bank2 Bank3 Bank4 Address Range 80'0000H - 9F'FFFFH A0'0000H - BF'FFFFH C0'0000H - DF'FFFFH E0'0000H - FF'FFFFH If a second ROM device is enabled, its base address depends on the maximum size of both ROM devices as defined within bit field SALSEL of register RP0H during reset. . Base Address of 2nd ROM Device SALSEL `111' `110' `101' `100' `011' others Physical Base Address 2nd ROM device not possible 20'0000H 10'0000H 08'0000H 04'0000H 02'0000H 4.5.3 Crossing Memory Boundaries The address space of M2 is implicitly divided into equally sized blocks of different granularity and into logical memory areas. Crossing the boundaries between these Users Manual 4 - 23 2000-06-15 SDA 6000 C16X Microcontroller blocks (code or data) or areas requires special attention to ensure that the controller executes the desired operations. Memory Areas are partitions of the address space that represent different kinds of memory (if provided at all). These memory areas are the internal RAM/SFR area, the program memory (if available), the on-chip X-Peripherals (if integrated) and the external memory. Accessing subsequent data locations that belong to different memory areas is no problem. However, when executing code, the different memory areas must be switched explicitly via branch instructions. Sequential boundary crossing is not supported and leads to erroneous results. Note: Changing from the external memory area to the internal RAM/SFR area takes place within segment 0. Segments are contiguous blocks of 64 KByte each. They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme. During code fetching segments are not changed automatically, but rather must be switched explicitly. The instructions JMPS, CALLS and RETS will do this. In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment, to prevent the prefetcher from trying to leave the current segment. Data Pages are contiguous blocks of 16 KByte each. They are referenced via the data page pointers DPP3...0 and via an explicit data page number for data accesses overriding the standard DPP scheme. Each DPP register can select one of the 1024 possible data pages. The DPP register that is used for the current access is selected via the two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16 KByte data page boundaries will therefore use different data page pointers, while the physical locations need not be subsequent within memory. 4.6 Central Processing Unit Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and to store the previously calculated results. Since a four stage pipeline is implemented in M2, up to four instructions can be processed in parallel. Most instructions of M2 are executed in one machine cycles (2 CPU clock cycles) due to this parallelism. This chapter describes how the pipeline works for sequential and branch instructions in general, and which hardware provisions have been made, in particular, to speed up the execution of jump instructions. The description of the general instruction timing includes standard and exceptional timing. For instruction and operand fetches, the CPU is connected to the different areas (external memory, program memory, internal dual-port RAM or (E)SFR area) either Users Manual 4 - 24 2000-06-15 SDA 6000 C16X Microcontroller internally or through the interfaces of the CPU (XBUS, program memory bus or peripheral bus). Where the program memory bus and the peripheral bus are tightly coupled to the CPU, XBUS accesses are performed, if possible, in parallel while the CPU continues operating. If data is required but not yet available or if a new XBUS access is requested by the CPU before a previous access has been completed, the CPU will be held until the request can be satisfied. CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. MCB02147 16 Internal RAM R15 General Purpose Registers R15 R0 R0 16 Figure 4-10 CPU Block Diagram Peripheral units are connected to the CPU by the peripheral bus or the XBUS and can work practically independent of the CPU. Data and control information is interchanged between the CPU and these peripherals by Special Function Registers (SFRs) or external memory locations, depending on to which bus they are connected. Whenever peripherals need a non-deterministic CPU action, the Interrupt Controller compares all pending peripheral service requests with each other and prioritizes one of them. If the priority of the current CPU operation is lower than the priority of the selected peripheral request, an interrupt will occur. Basically, there are two types of interrupt processing: * Standard interrupt processing forces the CPU to save the current program status and the return address to the stack before branching to the interrupt vector jump table. Users Manual 4 - 25 2000-06-15 SDA 6000 C16X Microcontroller * PEC interrupt processing steals just one machine cycle from the current CPU activity to perform a single data transfer via the on-chip Peripheral Event Controller (PEC). System errors detected during program execution (so-called hardware traps) are also processed as standard interrupts with a very high priority. Besides its normal operation there are the following particular CPU states: * Reset state: Any reset (hardware, software, watchdog) forces the CPU into a predefined active state. * IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the peripherals keep running. * POWER DOWN state: All of the on-chip clocks are switched off. A transition into an active CPU state is forced by an interrupt (if in IDLE mode) or by a reset (if in POWER DOWN mode). The IDLE, POWER DOWN and RESET states can be entered by particular system control instructions. A set of Special Function Registers is dedicated to the functions of the CPU core: * * * * * * * * General System Configuration: CPU Status Indication and Control: Code Access Control: Data Paging Control: GPRs Access Control: System Stack Access Control: Multiply and Divide Support: ALU Constants Support: SYSCON (RP0H) PSW IP, CSP DPP0, DPP1, DPP2, DPP3 CP SP, STKUN, STKOV MDL, MDH, MDC ZEROS, ONES 4.6.1 Instruction Pipelining The instruction pipeline of the CPU separates instruction processing into four stages, and each one has an individual task: 1st ->FETCH: In this stage the instruction selected by the Instruction Pointer (IP) and the Code Segment Pointer (CSP) is fetched from either the program memory, internal RAM, or external memory. 2nd ->DECODE: In this stage the instructions are decoded and, if required, the operand addresses are calculated and the respective operands are fetched. For all instructions, which implicitly access the system stack, the SP register is either decremented or incremented, as specified. For branch instructions the Instruction Pointer and the Code Segment Pointer are updated to the desired branch target address (provided that the branch is taken). Users Manual 4 - 26 2000-06-15 SDA 6000 C16X Microcontroller 3rd ->EXECUTE: In this stage an operation is performed on the previously fetched operands in the ALU. In addition, the condition flags in the PSW register are updated, as specified by the instruction. All explicit writes to the SFR memory space and all auto-increment or autodecrement writes to GPRs used as indirect address pointers are also performed during the execute stage of an instruction. 4th ->WRITE BACK: In this stage all external operands and the remaining operands within the internal RAM space are written back. A particularity of the CPU are the so-called imported instructions. These imported instructions are internally generated by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle. They are automatically imported into the decoding stage of the pipeline, and then they pass through the remaining stages like all standard instructions. Program interrupts are also performed by means of imported instructions. Although these internally imported instructions will not be noticed in reality, they are introduced here to ease the explanation of the pipeline in the following: Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are performed or not. Since passing through one pipeline stage takes at least one machine cycle, any isolated instruction takes at least four machine cycles to be completed. Pipelining, however, allows parallel (i.e. simultaneous) processing of up to four instructions. Thus, most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset (see Figure 4-11). Instruction pipelining increases the average instruction throughput considered over a certain period of time. In the following, any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing. Users Manual 4 - 27 2000-06-15 SDA 6000 C16X Microcontroller 1 Machine Cycle FETCH DECODE EXECUTE WRITEBACK Time UED11124 I1 I2 I1 I3 I2 I1 I4 I3 I2 I1 I5 I4 I3 I2 I6 I5 I4 I3 Figure 4-11 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed up sequential program processing. When a branch is taken, the instruction which has been fetched in advance is usually not the instruction which must be decoded next. Thus, at least one additional machine cycle is normally required to fetch the branch target instruction. This extra machine cycle is provided by means of an imported instruction (see Figure 4-12). 1 Machine Cycle FETCH DECODE EXECUTE WRITEBACK Time UED11125 Injection BRANCH I n+2 BRANCH I TARGET ( I INJECT) BRANCH I TARGET+1 I TARGET ( I INJECT) BRANCH I TARGET+2 I TARGET+1 I TARGET (I INJECT) I TARGET+3 I TARGET+2 I TARGET+1 I TARGET In ... ... In ... In Figure 4-12 Standard Branch Instruction Pipelining If a conditional branch is not taken, there is no deviation from the sequential program flow, and thus no extra time is required. In this case, the instruction following the branch instruction will enter the decoding stage of the pipeline at the beginning of the next machine cycle after decoding the conditional branch instruction. Users Manual 4 - 28 2000-06-15 SDA 6000 C16X Microcontroller Cache Jump Instruction Processing The CPU incorporates a jump cache to optimize conditional jumps, which are processed repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the branch target instruction can be saved, therefore causing the corresponding cache jump instruction to need only one machine cycle. This performance is achieved by the following mechanism: Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time (and provided that the jump condition is met), the jump target instruction is fetched as usual, causing a time delay of one machine cycle. In contrast to standard branch instructions, however, the target instruction of a cache jump instruction (JMPA, JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cache after having been fetched. After repeatedly following each execution of the same cache jump instruction, the jump target instruction is not fetched from program memory but taken from the cache and immediately imported into the decoding stage of the pipeline (see Figure 4-13). A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction, unless an instruction, which has the fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS, TRAP, RETI), or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction. Injection of Cached Target Instruction Injection 1 Machine Cycle FETCH DECODE EXECUTE WRITEBACK I n+2 Cache Jmp I TARGET ( I INJECT) Cache Jmp I TARGET+1 I TARGET (I INJECT) Cache Jmp I n+2 Cache Jmp I TARGET+1 I TARGET Cache Jmp I TARGET+2 I TARGET+1 I TARGET Cache Jmp In ... In ... In 1st Loop Iteration In Repeated Loop Iteration UED11126 Figure 4-13 Cache Jump Instruction Pipelining Particular Pipeline Effects Since up to four different instructions are processed simultaneously, additional hardware has been used in the CPU to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance. This extra hardware (i.e. for "forwarding" operand read and write values) resolves most of the Users Manual 4 - 29 2000-06-15 SDA 6000 C16X Microcontroller possible conflicts (e.g. multiple usage of buses) in a time optimized way and thus usually avoids the pipeline being noticed by the user. However, there are some very rare cases, where the CPU, being a pipelined machine, requires attention by the programmer. In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance. Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register, is mostly not capable of using a new CP value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new CP value is used, at least one instruction must be inserted between a CP-changing and a subsequent GPR-using instruction, as shown in the following example: In In+1 In+2 : SCXT CP, #0FC00h : .... : MOV R0, #dataX ; select a new context ; must not be an instruction using a GPR ; write to GPR 0 in the new context Data Page Pointer Updating An instruction, which calculates a physical operand address via a particular DPPn (n = 0 to 3) register, is mostly not capable of using a new DPPn register value, which is to be updated by an immediately preceding instruction. Thus, to make sure that the new DPPn register value is used, at least one instruction must be inserted between a DPPnchanging instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode, as shown in the following example: In In+1 In+2 : MOV : .... : MOV DPP0, #4 ; select data page 4 via DPP0 ; must not be an instruction using DPP0 DPP0:0000H, R1; move contents of R1 to address location 01'0000H ; (in data page 4) supposed segmentation is enabled Explicit Stack Pointer Updating None of the RET, RETI, RETS, RETP or POP instructions are capable of correctly using a new SP register value, which is to be updated by an immediately preceding instruction. Thus, in order to use the new SP register value without erroneously performed stack accesses, at least one instruction must be inserted between an explicitly SP-writing and any subsequent just mentioned implicitly SP-using instructions, as shown in the following example: In In+1 : MOV : .... SP, #0FA40H; select a new top of stack ; must not be an instruction popping operands ; from the system stack Users Manual 4 - 30 2000-06-15 SDA 6000 C16X Microcontroller In+2 : POP R0 ; pop word value from new top of stack into R0 Note: Conflicts with instructions writing to the stack (PUSH, CALL, SCXT) are solved internally by the CPU logic. Controlling Interrupts Software modifications (implicit or explicit) of the PSW are done in the execute phase of the respective instructions. In order to maintain fast interrupt responses, however, the current interrupt prioritization round does not consider these changes, i.e. an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the subsequent instructions. Timecritical instruction sequences therefore should not begin directly after the instruction disabling interrupts, as shown in the following example: BCLR IEN IN-1 CRIT_1ST: IN ... CRIT_LAST:IN+x INT_ON: BSET IEN INT_OFF: ; globally disable interrupts ; non-critical instruction ; begin of uninterruptable critical sequence ; end of uninterruptable critical sequence ; globally re-enable interrupts Note: The described delay of 1 instruction also applies for enabling the interrupts system i.e. no interrupt requests are acknowledged until the instruction after the enabling instruction. Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON (e.g. the mapping of the program memory, segmentation, stack size) cannot use the new resources (e.g. program memory or stack). In these cases an instruction that does not access these resources should be inserted. Code accesses to the new program memory area are only possible after an absolute branch to this area. Note: As a rule, instructions that change program memory mapping should be executed from internal RAM or external / XBUS memory. BUSCON/ADDRSEL and XBCON/XADRS The instruction following an instruction that changes the properties of an external / XBUS address area cannot access operands within the new area. In these cases an instruction that does not access this address area should be inserted. Code accesses to the new address area should be made after an absolute branch to this area. Note: As a rule, instructions that change external bus properties should not be executed from the respective external memory area. Users Manual 4 - 31 2000-06-15 SDA 6000 C16X Microcontroller Timing Instruction pipelining reduces the average instruction processing time on a wide scale (usually from four to one machine cycles). However, there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle. Although this additional time represents only a tiny part of the total program execution time, it might be of interest to avoid these pipeline-caused time delays in time critical program modules. Besides a general execution time description, the following section provides some hints on how to optimize time-critical program parts with regard to such pipeline-caused timing particularities. 4.6.2 Bit-Handling and Bit-Protection The CPU provides several mechanisms to manipulate bits. These mechanisms either manipulate software flags within the internal RAM, control on-chip peripherals via control bits in their respective SFRs or control IO functions via port pins. The instructions BSET, BCLR, BAND, BOR, BXOR, BMOV, BMOVN explicitly set or clear specific bits. The instructions BFLDL and BFLDH allow the manipulation of up to 8 bits of a specific byte at one time. The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken. The instructions JB and JNB (also conditional jump instructions that refer to flags) evaluate the specified bit to determine if the jump is to be taken. Note: Bit operations on undefined bit locations will always read a bit value of `0', while the write access will not effect the respective bit location. All instructions that manipulate single bits or bit groups internally use a read-modify-write sequence that accesses the whole word, which contains the specified bit(s). This method has several consequences: * Bits can only be modified within the internal address areas, i.e. internal RAM and SFRs. External locations cannot be used with bit instructions. The upper 256 bytes of the SFR area, the ESFR area and the internal RAM are bitaddressable (see Chapter 4.2), i.e. those register bits located within the respective sections can be directly manipulated using bit instructions. The other SFRs must be byte/word accessed. Note: All GPRs are bit-addressable independent of the allocation of the register bank via the context pointer CP. Even GPRs which are allocated to not bit-addressable RAM locations provide this feature. * The read-modify-write approach may be critical with hardware-effected bits. In these cases the hardware may change specific bits while the read-modify-write operation is in progress, where the writeback would overwrite the new bit value generated by the hardware. The solution is either the implemented hardware protection (see below) or Users Manual 4 - 32 2000-06-15 SDA 6000 C16X Microcontroller realization through special programming (see "Particular Pipeline Effects" on page 4-29). Protected bits are not changed during the read-modify-write sequence, i.e. when hardware sets e.g. an interrupt request flag between the read and the write of the readmodify-write sequence. The hardware protection logic guarantees that only the intended bit(s) is/are effected by the write-back operation. Note: If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit. 4.6.3 Instruction State Times Basically, the time needed to execute an instruction depends on where the instruction is fetched from, and where possible operands are read from or written to. The fastest processing mode of M2 is the execution of a program fetched from the program memory. In this case most of the instructions can be processed within just one machine cycle, which is also the general minimum execution time. This section summarizes the execution times in a very condensed way. A detailed description of the execution times for the various instructions and the specific exceptions can be found in the "C16x Family Instruction Set Manual". The table below shows the minimum execution times required to process an M2 instruction fetched from the program memory, the internal RAM or from external / XBUS memory. These execution times apply to most of the M2 instructions - except some of the branches, the multiplication, the division and a special move instruction. In case of program execution from the program memory there is no execution time dependency on the instruction length except for some special branch situations. The numbers in the table are in units of CPU clock cycles and assume no wait-states. Table 4-2 Minimum Execution Times Instruction Fetch Memory Area Internal code memory Internal RAM 16-bit Demux Bus 16-bit Mux Bus Word Instruction 2 6 2 3 Doubleword Instruction 2 8 4 6 Word Operand Access Read from 2 0/1 2 3 Write to - 0 2 3 Execution from the internal RAM provides flexibility in terms of loadable and modifiable code on the account of execution time. Users Manual 4 - 33 2000-06-15 SDA 6000 C16X Microcontroller Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles (wait-states). The operand and instruction accesses listed below can extend the execution time of an instruction: * * * * * * * Internal code memory operand reads (same for byte and word operand reads) Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing External operand reads External operand writes Jumps to non-aligned double word instructions in the program memory space Testing Branch Conditions immediately after PSW writes 4.6.4 CPU Special Function Registers The CPU requires a set of Special Function Registers (SFRs) to maintain the system state information, to supply the ALU with register-addressable constants and to control system and bus configuration, multiply and divide ALU operations, code memory segmentation, data memory paging, and accesses to the General Purpose Registers and the System Stack. The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR. Since all SFRs can simply be controlled by means of any instruction, which is capable of addressing the SFR memory space, a lot of flexibility has been gained, without the need to create a set of system-specific instructions. Note, however, that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations. The instruction pointer IP and code segment pointer CSP cannot be accessed directly. They can only be changed indirectly via branch instructions. The PSW, SP, and MDC registers can not only be modified explicitly by the programmer, but also implicitly by the CPU during normal instruction processing. Note that any explicit write request (via software) to an SFR supersedes a simultaneous modification by hardware of the same register. Note: Any write operation to a single byte of an SFR clears the non-addressed complementary byte within the specified SFR. Non-implemented (reserved) SFR bits cannot be modified, and will always supply a read value of '0'. System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT4 pins during reset. Users Manual 4 - 34 2000-06-15 SDA 6000 C16X Microcontroller SYSCON 15 14 13 12 ROM S1 Reset Value: 0400H 11 SGT DIS 10 ROM EN 9 - 8 - 7 - 6 CS CFG 5 - 4 - 3 RSO EN 2 XPEN 1 - 0 - STKSZ(2..0) rw Bit XPEN rw rw rw rw rw rw Function XBUS Peripheral Enable Bit `0': Accesses to the on-chip X-Peripherals and their functions are disabled. `1': The on-chip X-Peripherals are enabled and can be accessed. Reset Output Enable Bit `0': The contrast reduction signal is driven on pin 104. `1': The reset output signal is driven on pin 104, i.e. pin 104 is pulled low during internal reset sequence. RSOEN Note: Refer also to Chapter 6.7 CSCFG Select Line Configuration Control `0': Latched select line mode for X-Peripherals. `1': Select lines for access cycles via XBUS are directly derived from the address lines. Note: CSCFG = `1' is recommended. The effect of the switch is not visible at an external interface. ROMEN PM-Bus Enable Bit `0': PM-Bus disabled: accesses to the ROM area use the XBUS. `1': PM-Bus enabled: PM-Bus enabled for access cycles to the ROM area. Note: The recommended value ROMEN = `1' is set by hardware during reset. SGTDIS Segmentation Disable/Enable Control `0': Segmentation enabled (CSP is saved/restored during interrupt entry/exit). `1': Segmentation disabled (Only IP is saved/restored). Users Manual 4 - 35 2000-06-15 SDA 6000 C16X Microcontroller Bit ROMS1 Function Internal ROM Mapping `0': External ROM area mapped to segment 0 (00'0000H ... 00'7FFFH) `1': External ROM area mapped to segment 1 (01'0000H ... 01'7FFFH). Note: ROMS1 = `0' is recommended. STKSZ (2 ... 0) System Stack Size Selects the size of the system stack (in the internal RAM) from 32 to 1024 words. Note: Register SYSCON cannot be changed after execution of the EINIT instruction. Segmentation Disable/Enable Control (SGTDIS) Bit SGTDIS allows to select either the segmented or non-segmented memory mode. In non-segmented memory mode (SGTDIS = `1') it is assumed that the code address space is restricted to 64 KBytes (segment 0) and thus 16 bits are sufficient to represent all code addresses. For implicit stack operations (CALL or RET) the CSP register is totally ignored and only the IP is saved to and restored from the stack. In segmented memory mode (SGTDIS = `0') it is assumed that the whole address space is available for instructions. For implicit stack operations (CALL or RET) the CSP register and the IP are saved to and restored from the stack. After reset the segmented memory mode is selected. Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered, and it is repopped when the interrupt service routine is left again. System Stack Size (STKSZ) This bitfield defines the size of the physical system stack, which is located in the internal RAM of M2. An area of 32 ... 512 words or all of the internal RAM may be dedicated to the system stack. A so-called "circular stack" mechanism allows the use of a bigger virtual stack than this dedicated RAM area. The Processor Status Word PSW This bit-addressable register reflects the current state of the microcontroller. Two groups of bits represent the current ALU status, and the current CPU interrupt status. A separate bit (USR0) within register PSW is provided as a general purpose user flag. Users Manual 4 - 36 2000-06-15 SDA 6000 C16X Microcontroller PSW 15 14 13 12 11 IEN Reset Value: 0000H 10 HLD EN 9 - 8 - 7 - 6 USR0 5 MUL IP 4 E 3 Z 2 V 1 C 0 N ILVL(3..0) rw Bit N C V Z E MULIP rw Function rw rw rw rw rw rw rw rw Negative Result Set, when the result of an ALU operation is negative. Carry Flag Set, when the result of an ALU operation produces a carry bit. Overflow Result Set, when the result of an ALU operation produces an overflow. Zero Flag Set, when the result of an ALU operation is zero. End of Table Flag Set, when the source operand of an instruction is 8000H or 80H. Multiplication/Division In Progress `0': There is no multiplication/division in progress. `1': A multiplication/division has been interrupted. User General Purpose Flag May be used by the application software. Interrupt and EBC Control Fields Define the response to interrupt requests and enable external bus arbitration. USR0 HLDEN, ILVL, IEN ALU Status (N, C, V, Z, E, MULIP) The condition flags (N, C, V, Z, E) within the PSW indicate the ALU status after the last recently performed ALU operation. They are set by most of the instructions due to specific rules, which depend on the ALU or data movement operation performed by an instruction. After execution of an instruction which explicitly updates the PSW register, the condition flags cannot be interpreted as described in the following, because any explicit write to the PSW register supersedes the condition flag values, which are implicitly generated by the CPU. Explicitly reading the PSW register provides a read value that represents the state of the PSW register after execution of the immediately preceding instruction. Note: After reset, all of the ALU status bits are cleared. Users Manual 4 - 37 2000-06-15 SDA 6000 C16X Microcontroller * N-Flag: For most of the ALU operations, the N-flag is set to `1' if the most significant bit of the result contains a `1', otherwise it is cleared. In the case of integer operations the N-flag can be interpreted as the sign bit of the result (negative: N = `1', positive: N = `0'). Negative numbers are always represented as the 2's complement of the corresponding positive number. The range of signed numbers extends from `-8000H' to `+7FFFH' for the word data type, or from `-80H' to `+7FH' for the byte data type. For Boolean bit operations with only one operand, the N-flag represents the previous state of the specified bit. For Boolean bit operations with two operands, the N-flag represents the logical XORing of the two specified bits. * C-Flag: After an addition, the C-flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated. After a subtraction or a comparison, the C-flag indicates a borrow, which represents the logical negation of a carry for the addition. This means that the C-flag is set to `1' if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction, which is performed internally by the ALU as a 2's complement addition, and the C-flag is cleared when this complement addition causes a carry. The C-flag is always cleared for logical, multiply and divide ALU operations, because these operations cannot cause a carry. For shift and rotate operations the C-flag represents the value of the bit last shifted out. If a shift count of zero is specified, the C-flag will be cleared. The C-flag is also cleared for a prioritized ALU operation because a `1' is never shifted out of the MSB during the normalization of an operand. For Boolean bit operations with only one operand the C-flag is always cleared. For Boolean bit operations with two operands the C-flag represents the logical ANDing of the two specified bits. * V-Flag: For addition, subtraction and 2's complementation the V-flag is always set to `1', if the result overflows the maximum range of signed numbers, which are representable by either 16 bits for word operations (`-8000H' to `+7FFFH'), or by 8 bits for byte operations (`-80H' to `+7FH'), otherwise the V-flag is cleared. Note that the result of an integer addition, integer subtraction, or 2's complement is not valid if the V-flag indicates an arithmetic overflow. For multiplication and division the V-flag is set to `1' if the result cannot be represented in a word data type, otherwise it is cleared. Note that a division by zero will always cause an overflow. In contrast to the result of a division, the result of a multiplication is valid regardless of whether the V-flag is set to `1' or not. Since logical ALU operations cannot produce an invalid result, the V-flag is cleared by these operations. The V-flag is also used as a "Sticky Bit" for rotate right and shift right operations. By only using the C-flag, a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result. In conjunction with the Users Manual 4 - 38 2000-06-15 SDA 6000 C16X Microcontroller V-flag, the C-flag allows the evaluation of the rounding error with a finer resolution (see Table 4-3). For Boolean bit operations with only one operand the V-flag is always cleared. For Boolean bit operations with two operands the V-flag represents the logical ORing of the two specified bits. Table 4-3 C-Flag 0 0 1 1 Shift Right Rounding Error Evaluation V-Flag 0 1 0 1 Rounding Error Quantity - No rounding error 0 < Rounding error Rounding error Rounding error < 1/2 LSB = 1/2 LSB > 1/2 LSB * Z-Flag: The Z-flag is normally set to `1' if the result of an ALU operation equals zero, otherwise it is cleared. For the addition and subtraction with carry, the Z-flag is only set to `1' if the Z-flag already contains a `1' and the result of the current ALU operation additionally equals zero. This mechanism is provided for the support of multiple precision calculations. For Boolean bit operations with only one operand the Z-flag represents the logical negation of the previous state of the specified bit. For Boolean bit operations with two operands the Z-flag represents the logical NORing of the two specified bits. For the prioritized ALU operation the Z-flag indicates whether the second operand is zero or not. * E-Flag: The E-flag can be altered by instructions, which perform ALU or data movement operations. The E-flag is cleared by those instructions which cannot be reasonably used for table search operations. In all other cases the E-flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not. If the value of the source operand of an instruction equals the lowest negative number, which is representable by the data format of the corresponding instruction (`8000H' for the word data type, or `80H' for the byte data type), the E-flag is set to `1', otherwise it is cleared. * MULIP-Flag: The MULIP-flag will be set to `1' by hardware upon entry to an interrupt service routine, when a multiply or divide ALU operation was interrupted before completion. Depending on the state of the MULIP bit, the hardware decides whether multiplication or division must be continued or not after the end of an interrupt service. The MULIP bit is overwritten with the contents of the stacked MULIP-flag when the return-from-interrupt-instruction (RETI) is executed. This normally means that the MULIP-flag is cleared again after that. Note: The MULIP flag is a part of the task environment. When the interrupting service routine does not return to the interrupted multiply/divide instruction (i.e. as in the Users Manual 4 - 39 2000-06-15 SDA 6000 C16X Microcontroller case of a task scheduler that switches between independent tasks), the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered. CPU Interrupt Status (IEN, ILVL) The Interrupt Enable bit allows for global enabling (IEN = `1') or disabling (IEN = `0') of interrupts. The four-bit Interrupt Level field (ILVL) specifies the priority of the current CPU activity. The interrupt level is updated by hardware upon entry into an interrupt service routine, but it can also be modified via software to prevent other interrupts from being acknowledged. In case an interrupt level `15' has been assigned to the CPU, it has the highest possible priority, and thus the current CPU operation cannot be interrupted except by hardware traps or external non-maskable interrupts. For details please refer to Chapter 5. After reset all interrupts are globally disabled, and the lowest priority (ILVL = 0) is assigned to the initial CPU activity. The Instruction Pointer IP This register determines the 16-bit intra-segment address of the currently fetched instruction within the code segment selected by the CSP register. The IP register is not mapped into the M2's address space, and thus it is not directly accessible by the programmer. The IP can, however, be modified indirectly via the stack by means of a return instruction. The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations. IP 15 14 13 12 11 10 9 8 7 ip (15..0) 6 5 4 Reset Value: 0000H 3 2 1 0 r/w Bit ip(15 ... 0) Function Specifies the intra segment offset, from where the current instruction is to be fetched. IP refers to the current segment The Code Segment Pointer CSP This non-bit addressable register selects the code segment being used at run-time to access instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64 KBytes each, while the upper 8 bits are reserved for future use. Users Manual 4 - 40 2000-06-15 SDA 6000 C16X Microcontroller CSP 15 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 Reset Value: 0000H 3 2 1 0 SEGNR(7..0) Bit - - - - - - - r Function Segment Number Specifies the code segment, from where the current instruction is to be fetched. SEGNR is ignored when segmentation is disabled. SEGNR (7 ... 0) Code memory addresses are generated by directly extending the 16-bit contents of the IP register by the contents of the CSP register, as shown in Figure 4-14. In case of the segmented memory mode the selected number of segment address bits (via bit field SALSEL) of the CSP register is output on the respective segment address pins of Port 4 for all external code accesses. For non-segmented memory mode the content of this register is not significant, because all code accesses are automatically restricted to segment 0. Note: The CSP register can only be read but not written by data operations. It is, however, modified either directly by means of the JMPS and CALLS instructions, or indirectly via the stack by means of the RETS and RETI instructions. Upon the acceptance of an interrupt or the execution of a software TRAP instruction, the CSP register is automatically set to zero. Users Manual 4 - 41 2000-06-15 SDA 6000 C16X Microcontroller CSP Register Code Segment FF'FFFF H 255 254 FE'0000 H 15 0 15 IP Register 0 1 0 01'0000 H 00'0000 H 24/20/18-Bit Physical Code Address MCA02265 Figure 4-14 Addressing via the Code Segment Pointer Note: When segmentation is disabled, the IP value is used directly as the 16-bit address. The Data Page Pointers DPP0, DPP1, DPP2, DPP3 These four non-bit addressable registers select up to four different data pages being active simultaneously at run-time. The lower 10 bits of each DPP register select one of the 1024 possible 16-Kbyte data pages while the upper 6 bits are reserved for future use. The DPP registers allow access to the entire memory space in pages of 16 Kbytes each. DPP0 15 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 DPP0PN Reset Value: 0000H 3 2 1 0 DPP1 15 14 - 13 - 12 - 11 - 10 - rw 9 8 7 6 5 4 DPP1PN Reset Value: 0001H 3 2 1 0 - - - - - - rw Users Manual 4 - 42 2000-06-15 SDA 6000 C16X Microcontroller DPP2 15 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 DPP2PN Reset Value: 0002H 3 2 1 0 DPP3 15 14 - 13 - 12 - 11 - 10 - rw 9 8 7 6 5 4 DPP3PN Reset Value: 0003H 3 2 1 0 Bit - - - - - rw Function Data Page Number of DPPx Specifies the data page selected via DPPx. Only the least significant two bits of DPPx are significant, when segmentation is disabled. DPPxPN The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16-bit addressing modes (except for override accesses via EXTended instructions and PEC data transfers). After reset, the Data Page Pointers are initialized in a way that all indirect or direct long 16-bit addresses result in identical 18-bit addresses. This allows access to data pages 3 ... 0 within segment 0 as shown in the figure below. If the user does not want to use any data paging, no further action is required. Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16-bit address with the contents of the DPP register selected by the upper two bits of the 16-bit address. The contents of the selected DPP register specify one of the 1024 possible data pages. This data page base address, together with the 14-bit page offset, forms the physical 24-bit address (selectable part is driven to the address pins). In case of non-segmented memory mode, only the two least significant bits of the implicitly selected DPP register are used to generate the physical address. Thus, extreme care should be taken when changing the content of a DPP register if a nonsegmented memory model is selected, because otherwise unexpected results could occur. In case of the segmented memory mode the selected number of segment address bits (via bit field SALSEL) of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses. A DPP register can be updated via any instruction, which is capable of modifying an SFR. Users Manual 4 - 43 2000-06-15 SDA 6000 C16X Microcontroller Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the updating of the DPP register by the instruction. 16-Bit Data Address 15 14 0 1023 1022 1021 DPP Registers 3 2 1 0 DPP3-11 DPP2-10 DPP1-01 DPP0-00 14-Bit Intra-Page Address (concatenated with content of DPPx). Affer reset or with segmentation disabled the DPP registers select data pages 3...0. All of the internal memory is accessible in these cases. MCA02264 Figure 4-15 Addressing via the Data Page Pointers The Context Pointer CP This non-bit addressable register is used to select the current register context. This means that the CP register value determines the address of the first General Purpose Register (GPR) within the current register bank of up to 16 word and/or byte GPRs. CP 15 1 14 1 13 1 12 1 11 10 9 8 7 6 cp 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit cp r r r Function rw r Modifiable Portion of Register CP Specifies the (word) base address of the current register bank. When writing a value to register CP with bits CP.11 ... CP.9 = `000', bits CP.11 ... CP.10 are set to `11' by hardware, in all other cases all bits of bit field "cp" receive the written value. Users Manual 4 - 44 2000-06-15 SDA 6000 C16X Microcontroller Note: It is the user's responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location. If this condition is not met, unexpected results may occur. * Do not set CP below the IRAM start address, i.e. 00'FA00H/00'F600H/00'F200H (1/2/3KB) * Do not set CP above 00'FDFEH * Be careful when using the upper GPRs with CP above 00'FDE0H The CP register can be updated via any instruction which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register. The Switch Context instruction (SCXT) allows the saving of the contents of the CP register onto the stack and updating of it with a new value in just one machine cycle. Figure 4-16 Register Bank Selection via Register CP Several addressing modes use the CP register implicitly for address calculations. The addressing modes mentioned below are described in the "C16x Family Instruction Set Manual". Users Manual 4 - 45 2000-06-15 SDA 6000 C16X Microcontroller Short 4-Bit GPR Addresses (mnemonic: Rw or Rb) specify an address relative to the memory location specified by the contents of the CP register, i.e. the base of the current register bank. Depending on whether a relative word (Rw) or byte (Rb) GPR address is specified, the short 4-bit GPR address is sometimes multiplied by two before it is added to the contents of the CP register (see Figure 4-17). Thus, in this way, both byte and word GPR accesses are possible. GPRs used as indirect address pointers are always word accessed. For some instructions only the first four GPRs can be used as indirect address pointers. These GPRs are specified by short 2-bit GPR addresses. The respective physical address calculation is identical to that for the short 4-bit GPR addresses. Short 8-Bit Register Addresses (mnemonic: reg or bitoff), within a range from F0H to FFH, interpret the four least significant bits as short 4-bit GPR addresses, while the four most significant bits are ignored. The respective physical GPR address calculation is identical to that for the short 4-bit GPR addresses. For single bit accesses on a GPR, the GPR's word address is calculated as described above, but the position of the bit within the word is specified by a separate additional 4-bit value. Figure 4-17 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non-bit addressable register is used to point to the top of the internal system stack (TOS). The SP register is pre-decremented whenever data is to be pushed onto the stack, and it is post-incremented whenever data is to be popped from the stack. Thus, the system stack grows from higher to lower memory locations. Since the least significant bit of the SP register is tied to `0', and bits 15 through 12 are tied to `1' by hardware, the SP register can only contain values from F000H to FFFEH. This allows access to a physical stack within the internal RAM of the M2. A virtual stack Users Manual 4 - 46 2000-06-15 SDA 6000 C16X Microcontroller (usually bigger) can be realized via software. This mechanism is supported by the STKOV and STKUN registers (see respective descriptions below). The SP register can be updated via any instruction, which is capable of modifying an SFR. Note: Due to the internal instruction pipeline, a POP or RETURN instruction must not immediately follow an instruction updating the SP register. SP 15 1 14 1 13 1 12 1 11 10 9 8 7 6 sp 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit sp r r r Function rw r Modifiable portion of register SP Specifies the top of the internal system stack. The Stack Overflow Pointer STKOV This non-bit addressable register is compared against the SP register after each operation, which pushes data onto the system stack (e.g. PUSH and CALL instructions or interrupts) and after each subtraction from the SP register. If the contents of the SP register are less than the content of the STKOV register, a stack overflow hardware trap will occur. Since the least significant bit of register STKOV is tied to `0' and bits 15 through 12 are tied to `1' by hardware, the STKOV register can only contain values from F000H to FFFEH. STKOV 15 14 1 1 13 1 12 1 11 10 9 8 7 6 stkov 5 4 Reset Value: FA00H 3 2 1 0 0 r Bit stkov r r r Function rw r Modifiable portion of register STKOV Specifies the lower limit of the internal system stack. The Stack Overflow Trap (entered when (SP) < (STKOV)) may be used in two different ways: * Fatal error indication treats the stack overflow as a system error through the associated trap service routine. Under these circumstances data in the bottom of the Users Manual 4 - 47 2000-06-15 SDA 6000 C16X Microcontroller stack may have been overwritten by the status information stacked upon the stack overflow trap service. * Automatic system stack flushing allows the use of the system stack as a "Stack Cache" for a bigger external user stack. In this case the STKOV register should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size. This takes into consideration the worst case that could occur, when a stack overflow condition is only detected during entry into an interrupt service routine. Then, six additional stack word locations are required to push IP, PSW, and CSP for both the interrupt service routine and the hardware trap service routine. The Stack Underflow Pointer STKUN This non-bit addressable register is compared against the SP register after each operation, which pops data from the system stack (e.g. POP and RET instructions) and after each addition to the SP register. If the content of the SP register is greater than the content of the STKUN register, a stack underflow hardware trap will occur. Since the least significant bit of register STKUN is tied to `0' and bits 15 through 12 are tied to `1' by hardware, the STKUN register can only contain values from F000H to FFFEH. STKUN 15 14 1 1 13 1 12 1 11 10 9 8 7 6 stkun 5 4 Reset Value: FC00H 3 2 1 0 0 r Bit stkun r r r Function rw r Modifiable portion of register STKUN Specifies the upper limit of the internal system stack. The Stack Underflow Trap (entered when (SP) > (STKUN)) may be used in two different ways: * Fatal error indication treats the stack underflow as a system error through the associated trap service routine. * Automatic system stack refilling allows the use of the system stack as a "Stack Cache" for a bigger external user stack. In this case the STKUN register should be initialized to a value which represents the desired highest Bottom of Stack address. Scope of Stack Limit Control The stack limit control, realized by the register pair STKOV and STKUN, detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or Users Manual 4 - 48 2000-06-15 SDA 6000 C16X Microcontroller SUB instructions or by PUSH or POP operations (explicit or implicit, i.e. CALL or RET instructions). This control mechanism is not triggered, i.e. no stack trap is generated, when * the stack pointer SP is directly updated via MOV instructions * the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the new limits. The Multiply/Divide High Register MDH This register is a part of the 32-bit multiply/divide register, which is implicitly used by the CPU, when it performs a multiplication or a division. After a multiplication, this non-bit addressable register represents the high order 16 bits of the 32-bit result. For long division, the MDH register must be loaded with the high order 16 bits of the 32-bit dividend before the division is started. After any division, the MDH register represents the 16-bit remainder. MDH 15 14 13 12 11 10 9 8 7 mdh 6 5 4 Reset Value: 0000H 3 2 1 0 rw Bit mdh Function Specifies the high order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to `1'. When multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, the MDH register must be saved along with the MDL and MDC registers to avoid erroneous results. The Multiply/Divide Low Register MDL This register is a part of the 32-bit multiply/divide register which is implicitly used by the CPU when it performs a multiplication or a division. After multiplication, this non-bit addressable register represents the low order 16 bits of the 32-bit result. For long division, the MDL register must be loaded with the low order 16 bits of the 32-bit dividend before the division is started. After any division, the MDL register represents the 16-bit quotient. Users Manual 4 - 49 2000-06-15 SDA 6000 C16X Microcontroller MDL 15 14 Reset Value: 0000H 3 2 1 0 13 12 11 10 9 8 7 mdl 6 5 4 rw Bit mdl Function Specifies the low order 16 bits of the 32-bit multiply and divide register MD. Whenever this register is updated via software, the Multiply/Divide Register In Use (MDRIU) flag in the Multiply/Divide Control register (MDC) is set to `1'. The MDRIU flag is cleared whenever the MDL register is read via software. When multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine, the MDL register must be saved along with the MDH and MDC registers to avoid erroneous results. The Multiply/Divide Control Register MDC This bit addressable 16-bit register is implicitly used by the CPU when it performs multiplication or division. It is used to store the required control information for the corresponding multiply or divide operations. The MDC register is updated by hardware during each single cycle of a multiply or divide instruction. MDC 15 14 - 13 - 12 - 11 - 10 9 - 8 - 7 !! 6 !! 5 !! 4 MDR IU Reset Value: 0000H 3 2 1 0 !! !! !! !! Bit - - - - - - - r(w) r(w) r(w) r(w) r(w) r(w) r(w) r(w) Function Multiply/Divide Register In Use `0': Cleared, when register MDL is read via software. `1': Set when the MDL or MDH register is written via software, or when a multiply or divide instruction is executed. Internal Machine Status The multiply/divide unit uses these bits to control internal operations. Never modify these bits without saving and restoring the MDC register. MDRIU !! When division or multiplication is interrupted before its completion and the multiply/divide unit is required, the MDC register must first be saved along with the MDH and MDL Users Manual 4 - 50 2000-06-15 SDA 6000 C16X Microcontroller registers (to be able to restart the interrupted operation later), and then it must be cleared to prepare it for the new calculation. After the completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored. The MDRIU flag is the only portion of the MDC register which might be of interest to the user. The remaining portions of the MDC register are reserved for dedicated use by the hardware, and should never be modified by the user in any way other than described above. Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed. The Constant Zeros Register ZEROS All bits of this bit-addressable register are fixed to `0' by hardware. This register can be read only. The ZEROS register can be used as a register-addressable constant of all zeros, i.e. for bit manipulation or mask generation. It can be accessed via any instruction which is capable of addressing an SFR. ZEROS 15 14 0 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 Reset Value: 0000H 3 2 1 0 0 0 0 0 r r r r r r r r r r r r r r r r The Constant Ones Register ONES All bits of this bit-addressable register are fixed to `1' by hardware. This register can be read only. The ONES register can be used as a register-addressable constant of all ones, i.e. for bit manipulation or mask generation. It can be accessed via any instruction which is capable of addressing an SFR. ONES (FF1EH / 8FH) 15 14 13 12 11 1 1 1 1 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 Reset Value: FFFFH 3 2 1 0 1 1 1 1 r r r r r r r r r r r r r r r r Note: Register SYSCON cannot be changed after execution of the EINIT instruction. Identification Register Block All new derivatives of 16-bit microcontrollers provide a set of identification registers that offer information on the HW-status of the chip.The ID registers are read only registers. They are placed in the extended SFR area. Users Manual 4 - 51 2000-06-15 SDA 6000 C16X Microcontroller IDCHIP 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID(7..0) CHIPREVNU(7..0) r Bit CHIPREVNU (7 ... 0) CHIPID (7 ... 0) IDMANUF 15 14 13 Function r Device Revision Code Identifies the device step where the first release is marked `01H'. Device Identification Identifies the device name. 12 11 10 9 8 7 6 5 4 3 - 2 - 1 - 0 - MANUF r Bit MANUF Function JEDEC Normalized Manufacturer Code 0C1H: Infineon Technologies Users Manual 4 - 52 2000-06-15 Interrupt and Trap Function SDA 6000 Interrupt and Trap Functions 5 Interrupt and Trap Functions The C166 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources either by the CPU itself or external, i.e. peripherals connected to the XBUS or the PD bus. These mechanisms include: Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches to an interrupt service routine in order to service an interrupt requesting device. The current program status (IP, PSW, also CSP in segmentation mode) is saved on the internal system stack. A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled. Interrupt Processing via the Peripheral Event Controller (PEC) A faster alternative to normal software controlled interrupt processing is to service an interrupt requesting device with the integrated Peripheral Event Controller (PEC). Triggered by an interrupt request, the PEC performs a single word or byte data transfer between any two locations in the whole memory space through one of nine programmable PEC Service Channels. During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle. No internal program status information needs to be saved. The same prioritization scheme is used for PEC service as for normal interrupt processing. PEC transfers share the 2 highest priority levels. M2 enhances the functionalities of the original C166 PEC with the following features: * PEC range extended to the entire memory space, * new chaining mechanism between pairs of PEC channels. Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions. Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction. Hardware traps always have highest priority and cause immediate system reaction. The software trap function is invoked by the TRAP instruction, which generates a software interrupt for a specified interrupt vector. For all types of traps the current program status is saved on the system stack. 5.1 Interrupt System Structure M2 provides up to 33 separate interrupt nodes that may be assigned to 16 priority levels. Each node is associated with an interrupt input line in the Interrupt System Interface of the CPU. In order to support modular and consistent software design techniques, all Users Manual 5-3 2000-06-15 SDA 6000 Interrupt and Trap Functions interrupt nodes are supplied with a separate interrupt control register and interrupt vector. The control register contains the interrupt request flag, the interrupt enable bit, and the interrupt priority of the associated node. The C166 architecture provides a vectored interrupt system. In this system specific vector locations in the memory space are reserved for the reset, trap, and interrupt service functions. Whenever a request occurs, the CPU branches to the location that is associated with the respective interrupt source. This allows direct identification of the source that caused the request. The only exceptions are the class B hardware traps, which all share the same interrupt vector. The status flags in the Trap Flag Register (TFR) can then be used to determine which exception caused the trap. For the special software TRAP instruction, the vector address is specified by the operand field of the instruction, which is a seven bit trap number. The reserved vector locations build a jump table in the low end of the address space (segment 0). The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines, which may be located anywhere within the address space. The entries of the jump table are located at the lowest addresses in code segment 0 of the address space. Each entry occupies 2 words, except for the reset vector and the hardware trap vectors which occupy 4 or 8 words. 5.1.1 Interrupt Allocation Table M2 provides 33 separate interrupt nodes that may be assigned to 16 priority levels. In addition to the standard peripheral and external interrupts, there are some teletext related interrupts which support the realtime processing of the sliced data and the generation of the graphical data. Its fast external interrupt inputs are sampled every 3 ns and are even able to recognize very short external signals. The Table 5-1 lists all sources that are capable of requesting interrupt or PEC service in M2, the associated interrupt vectors, their locations and the associated trap numbers. It also lists the mnemonics of the affected interrupt request flags and their corresponding interrupt enable flags. The mnemonics are composed of a part that specifies the respective source, followed by a part that specifies their function (IR = Interrupt Request flag, IE = Interrupt Enable flag). Table 5-1 Interrupt Allocation Table Interrupt Control Register EX0IC EX1IC EX2IC EX3IC 5-4 Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 Users Manual Address of Interrupt Control Vector Register Location 00'FF88H 00'FF8AH 00'FF8CH 00'FF8EH 00'0060H 00'0064H 00'0068H 00'006CH Trap Number 18H/24D 19H/25D 1AH/26D 1BH/27D 2000-06-15 SDA 6000 Interrupt and Trap Functions Table 5-1 Interrupt Allocation Table (cont'd) Interrupt Control Register EX4IC EX5IC EX6IC EX7IC T2IC T3IC T4IC T5IC T6IC CRIC ADC1IC ADC2IC S0TIC S0TBIC S0RIC Address of Interrupt Control Vector Register Location 00'FF90H 00'FF92H 00'FF94H 00'FF96H 00'FF60H 00'FF62H 00'FF64H 00'FF66H 00'FF68H 00'FF6AH 00'FF98H 00'FF9AH 00'FF6CH 00'F19CH 00'FF6EH 00'FF9EH 00'F17AH 00'FF70H 00'FF72H 00'FF74H 00'FF76H 00'F194H 00'F18CH 00'F184H 00'F178H 00'F176H 00'F174H 00'F172H 00'FF9CH 5-5 Source of Interrupt or PEC Service Request External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A/D1 Conversion Complete A/D2 Conversion Complete ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive Trap Number 1CH/28D 1DH/29D 1EH/30D 1FH/31D 22H/34D 23H/35D 24H/36D 25H/37D 26H/38D 27H/39D 28H/40D 29H/40D 2AH/42D 47H/71D 2BH/43D 21H/33D 3DH/61D 2CH/44D 2DH/45D 2EH/46D 2FH/47D 46H/70D 45H/69D 44H/68D 3CH/60D 3BH/59D 3AH/58D 39H/57D 20H/32D 2000-06-15 00'0070H 00'0074H 00'0078H 00'007CH 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'0084H 00'00F4H 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0118H 00'0114H 00'0110H 00'00F0H 00'00ECH 00'00E8H 00'00E4H 00'0080H ASC0 Autobaud Detection Start ABSTAIC ASC0 Autobaud Detection Stop ABSTOIC ASC0 Error SSC Transmit SSC Receive SSC Error I2C Data Transfer Event I2C Protocol Event I2C Transmission End Event ADC Wake Up ACQ Interrupt * Display Vertical Sync * Display Horizontal Sync * Graphic Acc. Finished * Users Manual S0EIC SSCTIC SSCRIC SSCEIC I2CTIC I2CPIC I2CTEIC ADWIC ACQIC VSDISIC HSDISIC GAFIC SDA 6000 Interrupt and Trap Functions Table 5-1 Interrupt Allocation Table (cont'd) Interrupt Control Register RTCIC PECCLIC Address of Interrupt Control Vector Register Location 00'F19EH 00'F180H 00'010CH 00'004CH Trap Number 43H/67D 4CH/76D Source of Interrupt or PEC Service Request Realtime Clock PECC Link IRQ Note: Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction. The respective vector location results from multiplying the trap number by 4 (4 bytes per entry). Note: * = Interrupts relevant for acquisition and graphic support. 5.1.2 Hardware Traps The Table 5-2 lists the vector locations for hardware traps and the corresponding status flags in the TFR register. It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction. After any reset, program execution starts at the reset vector at location 00'0000H. Reset conditions have priority over every other system activity and therefore have the highest priority (trap priority IV). Software traps may be initiated to any vector location between 00'0000H and 00'01FCH. A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW. This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests. Table 5-2 Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Debug Hardware Trap Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Trap Flag - Trap Vector RESET RESET RESET DTRAP Vector Location 00'0000H 00'0000H 00'0000H 00'0020H Trap Number 00H 00H 00H 08H 02H 04H 06H Trap Priority IV IV IV III II II II DEBUG NMI STKOF STKUF NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H Users Manual 5-6 2000-06-15 SDA 6000 Interrupt and Trap Functions Table 5-2 (cont'd) Trap Flag Trap Vector Vector Location 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H Trap Number 0AH 0AH 0AH 0AH 0AH Trap Priority I I I I I Exception Condition Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction UNDOPC BTRAP PRTFLT BTRAP ILLOPA ILLINA ILLBUS - - BTRAP BTRAP BTRAP - - [2CH - 3CH] [0BH - 0FH] - Any Any Current [00'0000H - [00H - 7FH] CPU 00'01FCH] Priority in steps of 4H Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority. This prioritization of interrupts and PEC requests is programmable in two levels. Each requesting source can be assigned to a specific priority. A second level (called "group priority") allows the specification of an internal order for simultaneous requests from a group of different sources on the same priority level. At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system. This request will then be serviced if its priority is higher than the current CPU priority in the PSW register. Interrupt System Register Description Interrupt processing is controlled globally by the PSW register through a general interrupt enable bit (IEN) and the CPU priority field (ILVL). Additionally the different interrupt sources are controlled individually by their specific interrupt control registers (... IC). Thus, the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW. PEC services are controlled by the respective PECCx register and the source and destination pointers, which specify the task of the respective PEC service channel. Users Manual 5-7 2000-06-15 SDA 6000 Interrupt and Trap Functions Interrupt Control Registers All interrupt control registers are organized identically. The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization; the upper 8 bits of the respective register are reserved. All interrupt control registers are bit-addressable and all bits can be read or written via software. This allows each interrupt source to be programmed or modified with just one instruction. When accessing interrupt control registers through instructions which operate on word data types, their upper 8 bits (15 ... 8) will return zeros when read, and will discard written data. Note: The layout of the Interrupt Control registers shown below applies to each xxIC register, where xx stands for the mnemonic for the respective source. Interrupt Node Sharing The interrupt controller of M2 can be configured to control up to 33 different sources. If there is a need for a greater number of interrupt sources to be managed, interrupt requests may share the same interrupt node. In this case, all the sources on the same node share the priority level defined by the corresponding Interrupt Control register xxIC and may be globally enabled/disabled by the IE bit of this register. Arbitration between sources connected to the same node must be performed by the interrupt handler associated with this node. For low rate requests, the software overhead is not critical. Users Manual 5-8 2000-06-15 SDA 6000 Interrupt and Trap Functions xxIC 15 14 13 12 11 10 9 8 7 xxIR Reset Value: - - 00H 6 xxIE 5 4 ILVL 3 2 1 GLVL 0 - - - - - - - - rw rw rw rw Bit GLVL Function Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests. FH: Highest priority level 0H: Lowest priority level Interrupt Enable Control Bit (individually enables/disables a specific source) `0': Interrupt request is disabled `1': Interrupt Request is enabled Interrupt Request Flag `0': No request pending `1': This source has raised an interrupt request ILVL xxIE xxIR The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs. It is cleared automatically upon entry into the interrupt service routine or upon a PEC service. In the case of PEC service, the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel decrements to zero. This allows a normal CPU interrupt to respond to a completed PEC block transfer. Note: Modifying the Interrupt Request flag via software causes the same effect as if it had been set or cleared by hardware. Interrupt Priority Level and Group Level The four bits of an ILVL bit field specify the priority level of a service request for the arbitration of simultaneous requests. The priority increases with the numerical value of ILVL, so 0000B is the lowest and 1111B is the highest priority level. When more than one interrupt request on a specific level becomes active at the same time, the values in the respective GLVL bit fields are used for second level arbitration to select one request for servicing. Again the group priority increases with the numerical value of GLVL, so 00B is the lowest and 11B is the highest group priority. Users Manual 5-9 2000-06-15 SDA 6000 Interrupt and Trap Functions Note: All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities. Otherwise an incorrect interrupt vector will be generated. Upon entry into the interrupt service routine the priority level of the source that won the arbitration and who's priority level is higher than the current CPU level, is copied into the ILVL bit field of register PSW after pushing the old PSW contents onto the stack. The interrupt system of M2 allows nesting of up to 15 interrupt service routines of different priority levels (level 0 cannot be arbitrated). Interrupt requests that are programmed to priority levels 15 or 14 (i.e., ILVL = 111XB) will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero. In this case the request will instead be serviced by normal interrupt processing. Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing. Note: Priority level 0000B is the default level of the CPU. Therefore a request on level 0 will never be serviced, because it can never interrupt the CPU. However, an enabled interrupt request on level 0000B will terminate the Idle mode and reactivate the CPU. For interrupt requests which are to be serviced by the PEC, the associated PEC channel number is derived from the respective ILVL (LSB) and GLVL (see Figure 5-1). So programming a source to priority level 15 (ILVL = 1111B) selects the PEC channel group 7 ... 4, programming a source to priority level 14 (ILVL = 1110B) selects the PEC channel group 3 ... 0. The actual PEC channel number is then determined by the GLVL group priority field. Interrupt Control Register ILVL GLVL PEC Control PEC Channel # UED11127 Figure 5-1 Priority Levels and PEC Channels Simultaneous requests for PEC channels are prioritized according to the PEC channel number, where channel 0 has lowest and channel 8 has highest priority. Note: All sources that request PEC service must be programmed to different PEC channels. Otherwise an incorrect PEC channel may be activated. Users Manual 5 - 10 2000-06-15 SDA 6000 Interrupt and Trap Functions The table below shows a few examples of each action executed with each particular programming of an interrupt control register. Priority Level ILVL 1111 1111 1110 1101 0001 0001 0000 GLVL 11 10 10 10 11 00 XX COUNT = 00H CPU interrupt, level 15, group priority 3 CPU interrupt, level 15, group priority 2 CPU interrupt, level 14, group priority 2 CPU interrupt, level 13, group priority 2 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 0 No service! Type of Service COUNT 00H PEC service, channel 7 PEC service, channel 6 PEC service, channel 2 CPU interrupt, level 13, group priority 2 CPU interrupt, level 1, group priority 3 CPU interrupt, level 1, group priority 0 No service! Note: All requests on levels 13 ... 1 cannot initiate PEC transfers. They are always serviced by an interrupt service routine. No PECC register is associated and no COUNT field is checked. Interrupt Control Functions in the PSW The Processor Status Word (PSW) is functionally divided into 2 parts: the lower byte of the PSW basically represents the arithmetic status of the CPU, the upper byte of the PSW controls the interrupt system of M2 and the arbitration mechanism for the external bus interface. Note: Pipeline effects have to be considered when enabling/disabling interrupt requests via modifications of register PSW. Users Manual 5 - 11 2000-06-15 SDA 6000 Interrupt and Trap Functions PSW 15 14 13 12 11 IEN rw 10 HLD EN rw 9 8 7 6 USR0 rw 5 MUL IP rw 4 E rw Reset Value: 0000H 3 Z rw 2 V rw 1 C rw 0 N rw ILVL rw Bit Function N, C, V, Z, E, CPU status flags (Described in Chapter 4.6) MULIP, Define the current status of the CPU (ALU, multiplication unit). USR0 HLDEN HOLD Enable (Enables External Bus Arbitration) 0: Bus arbitration disabled, P6.7 ... P6.5 may be used for general purpose IO 1: Bus arbitration enabled, P6.7 ... P6.5 serve as BREQ, HLDA, HOLD, resp. CPU Priority Level Defines the current priority level for the CPU FH: Highest priority level 0H: Lowest priority level Interrupt Enable Control Bit (globally enables/disables interrupt requests) `0': Interrupt requests are disabled `1': Interrupt requests are enabled ILVL IEN CPU Priority ILVL defines the current level for the operation of the CPU. This bit field reflects the priority level of the routine that is currently being executed. Upon entry into an interrupt service routine, this bit field is updated with the priority level of the request that is being serviced. The PSW is saved on the system stack before. The CPU level determines the minimum interrupt priority level that will be serviced. Any request on the same or lower level will not be acknowledged. The current CPU priority level may be adjusted via software, to control which interrupt request sources will be acknowledged. PEC transfers do not really interrupt the CPU, but rather "steal" a single cycle, so PEC services do not influence the ILVL field in the PSW. Hardware traps switch the CPU level to maximum priority (i.e. 15) so no interrupt or PEC requests will be acknowledged while an exception trap service routine is being executed. Note: The TRAP instruction does not change the CPU level, so software invoked trap service routines may be interrupted by higher requests. Interrupt Enable bit IEN globally enables or disables PEC operations and the acceptance of interrupts by the CPU. When IEN is cleared, no new interrupt requests Users Manual 5 - 12 2000-06-15 SDA 6000 Interrupt and Trap Functions are accepted by the CPU. However requests that have already entered the pipeline at that time will be processed. When IEN is set to `1', all interrupt sources, which have been individually enabled by the interrupt enable bits in their associated control registers, are globally enabled. Note: Traps are non-maskable and are therefore not affected by the IEN bit. 5.2 Operation of the PEC Channels M2's Peripheral Event Controller (PEC) provides 8 PEC service channels, which move a single byte or word between two locations in the entire memory space. Packet transfers are provided with channels 0 and 1. This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request (e.g. serial channels, etc.). Each channel is controlled by a dedicated PEC Channel Counter/Control register (PECCx) and a pair of pointers for the source (SRCPx) and destination (DSTPx) of the data transfer. The PECC registers control the action that is performed by the respective PEC channel. Compared to existing C16x architectures, the PEC transfer function is enhanced by extended functionality. The extended PEC functions are defined as follows: * Source pointer and destination pointer are extended to 24-bit pointer, thus enabling PEC controlled data transfers between any two locations within the total address space. Both 8-bit segment numbers of every source/destination pointer pair are defined in one 16-bit SFR register; thus, 8 PEC segment number registers are available for the 8 PEC channels. * For every two channels a chaining feature is provided. When enabled in the PEC control register, a termination interrupt of one channel will automatically switch transfer control to the other channel of the channel pair. Extended PEC Channel Control The PEC control registers with the extended functionality and their application for new PEC control are defined as follows: Users Manual 5 - 13 2000-06-15 SDA 6000 Interrupt and Trap Functions PECCx 15 - Reset Value: 0000H 13 - 14 - 12 CLT 11 CL 10 9 8 BWT 7 6 5 4 3 2 1 0 INC(1..0) COUNT (7...0) rw rw rw rw rw Bit COUNT (7 ... 0) BWT Function PEC Transfer Count Counts PEC transfers (bytes or words) and influences the channel's action. Byte / Word Transfer Selection 0: Transfer a Word. 1: Transfer a Byte. Increment Control (Modification of SRCPx or DSTPx) 0 0: Pointers are not modified. 0 1: Increment DSTPx by 1 or 2. 1 0: Increment SRCPx by 1 or 2. 1 1: Reserved. Do not use this combination. Channel Link Control 0: PEC channels work independent 1: Pairs of channels are linked together Channel Link Toggle State 0: Even numbered PEC channel of linked channels active 1: Odd numbered PEC channel of linked channels active INC(1 ... 0) CL CLT Table 5-3 Register PECC0 PECC1 PECC2 PECC3 PEC Control Register Addresses Address FEC0H / 60H FEC2H / 61H FEC4H / 62H FEC6H / 63H Reg. Space SFR SFR SFR SFR Register PECC4 PECC5 PECC6 PECC7 Address FEC8H / 64H FECAH / 65H FECCH / 66H FECEH / 67H Reg. Space SFR SFR SFR SFR Byte/Word Transfer bit BWT controls, if a byte or a word is moved during a PEC service cycle. This selection controls the transferred data size and the increment step for the modified pointer. Users Manual 5 - 14 2000-06-15 SDA 6000 Interrupt and Trap Functions Increment Control Field INC controls, if one of the PEC pointers is incremented after the PEC transfer. However, it is not possible to increment both pointers. If the pointers are not modified (INC = `00') the respective channel will always move data from the same source to the same destination. Note: The reserved combination `11' is changed to `10' by hardware. However, it is not recommended to use this combination. The PEC Transfer Count Field COUNT controls the action of a respective PEC channel, where the content of bit field COUNT, at the time the request is activated, selects the action. COUNT may allow a specified number of PEC transfers, unlimited transfers or no PEC service at all. The table below summarizes, how the COUNT field itself, the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT. Previous COUNT FFH Modified COUNT FFH IR after PEC Action of PEC Channel service and Comments `0' Move a Byte / Word Continuous transfer mode, i.e. COUNT is not modified Move a Byte / Word and decrement COUNT Move a Byte / Word Leave request flag set, which triggers another request No action! Activate interrupt service routine rather than PEC channel. FEH ... 02H FDH ... 01H `0' 01H 00H `1' 00H 00H (`1') The PEC transfer counter allows the servicing of a specified number of requests by the respective PEC channel, and then (when COUNT reaches 00H) activates the interrupt service routine, which is associated with the priority level. After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced. Continuous transfers are selected by the value FFH in bit field COUNT. In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again. When COUNT is decremented from 01H to 00H after a transfer the request flag is not cleared, which generates another request from the same source. When COUNT already contains the value 00H, the respective PEC channel remains idle and the associated interrupt service routine is activated instead. This provides a choice if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine. Users Manual 5 - 15 2000-06-15 SDA 6000 Interrupt and Trap Functions Note: PEC transfers are only executed if their priority level is higher than the CPU level, i.e. only PEC channels 7 ... 4 are processed, while the CPU executes on level 14. All interrupt request sources that are enabled and programmed for PEC service should use different channels. Otherwise only one transfer will be performed for all simultaneous requests. When COUNT is decremented to 00H, and the CPU is interrupted, an incorrect interrupt vector will be generated. Channel Link Mode for Data Chaining Data chaining with linked PEC channels is enabled if the channel link control bit in PECCx register is set to `1' either in one or both PEC channel control registers of a channel pair. In this case, two PEC channels are linked together and handle chained block transfers alternatively to each other. The whole data transfer is divided into several block transfers where each block is controlled by one PEC channel of a channel pair. When a data block is completely transferred a channel link interrupt is generated and the PEC service request processing is automatically switched to the "other" PEC channel of the channel-pair. Thus, PEC service requests addressed to a linked PEC channel are either handled by linked PEC channel A or by linked PEC channel B. This channel toggle allows the setting up of shadow and multiple buffers for PEC transfers by changing pointer and count values of one channel while the other channel is active. The following table lists the channels that can be linked together, and the channel numbers to address the linked channels. Linked PEC Channels PEC Channel A channel 0 channel 2 channel 4 channel 6 PEC Channel B channel 1 channel 3 channel 5 channel 7 channel 0 channel 2 channel 4 channel 6 Linked PEC Channel For each pair of linked channels an internal channel flag, the channel link toggle flag CLT, identifies which of the two PEC channels will serve the next PEC request. The CLT flag is indicated in both PECCx registers of the two linked PEC channels, where the CLT bit in channel B is always inverse to the CLT bit in channel A. The very first transfer is always started with the channel A if the CLT bit is not otherwise programmed before. The CLT bit is only valid in the case of linked PEC channels, indicated by the CL bits of linked channels. If linking is not enabled, the CLT bit of both channels is always zero. The internal channel link flag CLT toggles, and the other channel begins servicing with the next request if the "old" channel stops the service (COUNT = 0), and if the new Users Manual 5 - 16 2000-06-15 SDA 6000 Interrupt and Trap Functions channel has in its PEC control register the enabled CL flag and if its transfer count is more than zero. Note: With the last transfer of a block transfer (COUNT = 0), the channel link control flag CL of that channel is cleared in its PECCx register. If the CL channel link flag of the new (chained) PEC control register is found to be zero, the whole data transfer is finished and the channel link interrupt is coincidentally a termination interrupt. The channel link mode is finished and the internal channel toggle flag is cleared after the last transfer of the block, if the CL flags of both pair channels are cleared. Additional Interrupt Request Node for Channel Link Interrupts The PEC unit has one dedicated service request node (trap number) for all channel link interrupts. This service request node requests CPU interrupt service in case of one or more channel link request flags and the respective enable control bit being set in the channel link interrupt subnode control register (CLISNC). These flags indicate a channel link interrupt condition of linked PEC channels (A and B channels) which requires support from the CPU. The following channel link interrupt conditions requesting CPU service are possible: * In single transfer mode a COUNT value change from 01H to 00H in a linked PEC channel and CL flag is set in the respective PEC control register. In this case the CPU service is requested to update the PEC control and pointer registers while the next block transfer is executed (the whole transfer is divided into separately controlled block transfers). The last block transfer is determined by the missing link bit in the new (linked) PEC control register. If a new service request hits a linked channel with count equal to zero and channel link flag disabled, a standard interrupt, as known from standard PEC channels, is performed. The channel link interrupt subnode register CLISNC is defined as follows: Users Manual 5 - 17 2000-06-15 SDA 6000 Interrupt and Trap Functions CLISNC 15 - Reset Value: 0000H 13 C6 IR 14 - 12 C6 IE 11 - 10 - 9 C4 IR 8 C4 IE 7 - 6 - 5 C2 IR 4 C2 IE 3 - 2 - 1 C0 IR 0 C0 IE rw Bit xxIE rw Function rw rw rw rw rw rw PEC Channel Link Interrupt Enable Control Bit (individually enables/disables a specific channel pair interrupt request) `0': PEC interrupt request is disabled `1': PEC interrupt request is enabled PEC Channel Service Request Flag `0': No channel link service request pending `1': This source (channel pair) has raised an request to service a PEC channel after channel linking xxIR The source and destination pointers specifiy the locations between which the data is to be moved. PEC transfers can be performed between any locations in the entire memory space of the M2. For each of the 8 PEC channels, the source and destination addresses are specified by a 8-bit segment number and a 16-bit offset. The source and destination segment numbers, respectively PECSSN and PECDSN, are stored in a SFR associated with each channel (PECSNx, see description below). The offset pointers for the source and destination address do not reside in specific SFRs, but are mapped into the internal RAM of the M2 just below the bit-addressable area (see Figure 5-2). Users Manual 5 - 18 2000-06-15 SDA 6000 Interrupt and Trap Functions DSTP7 SRCP7 DSTP6 SRCP6 DSTP5 SRCP5 DSTP4 SRCP4 00'FCFE H 00'FCFC H 00'FCFA H 00'FCF8 H 00'FCF6 H 00'FCF4 H 00'FCF2 H 00'FCF0 H DSTP3 SRCP3 DSTP2 SRCP2 DSTP1 SRCP1 DSTP0 SRCP0 00'FCEE H 00'FCEC H 00'FCEA H 00'FCE8 H 00'FCE6 H 00'FCE4 H 00'FCE2 H 00'FCE0 H UED11128 Figure 5-2 Mapping of PEC Offset Pointers into the Internal RAM The pointer locations for inactive PEC channels may be used for general data storage. Only the required pointers occupy RAM locations. PECSNx 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 PECDSN (7...0) PECSSN (7...0) rw Bit PECSSN (7 ... 0) PECDSN (7 ... 0) Function rw PEC Source Segment Number 8-bit Segment Number (address bits A23 ... 16) used for addressing the source of the respective PEC transfer. PEC Destination Segment Number 8-bit Segment Number (address bits A23 ... 16) used for addressing the destination of the respective PEC transfer. Users Manual 5 - 19 2000-06-15 SDA 6000 Interrupt and Trap Functions Table 5-4 Register PECSN0 PECSN1 PECSN2 PECSN3 PEC Segment Number Register Addresses Address FED0H / 68H FED2H / 69H FED4H / 6AH FED6H / 6BH Reg. Space SFR SFR SFR SFR Register PECSN4 PECSN5 PECSN6 PECSN7 Address Reg. Space FED8H / 6CH SFR FEDAH / 6DH SFR FEDCH / 6EH SFR FEDEH / 6FH SFR If a word data transfer is selected for a specific PEC channel (i.e. BWT = `0'), the respective source and destination pointers must both contain a valid word address which points to an even byte boundary. Otherwise the Illegal Word Access trap will be invoked when this channel is used. 5.2.1 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced (if they win), or they may be disabled so their requests are disregarded and not serviced. Enabling and disabling interrupt requests may be done via three mechanisms: Control Bits allow the switching of each individual source to "ON" or "OFF" so that it may generate a request or not. The control bits (xxIE) are located in the respective interrupt control registers. All interrupt requests can generally be enabled or disabled via the IEN bit in register PSW. This control bit is the "main switch" that selects whether requests from any source are accepted or not. For a specific request to be arbitrated the respective source's enable bit and the global enable bit must both be set. The Priority Level automatically selects a certain group of interrupt requests that will be acknowledged, disclosing all other requests. The priority level of the source that won the arbitration is compared with the CPU's current level and the source is only serviced if its level is higher than the current CPU level. Changing the CPU level to a specific value via software blocks all requests on the same or a lower level. An interrupt source that is assigned to level 0 will be disabled and never be serviced. The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 ... 4 instructions. This is useful e.g. for semaphore handling and does not require re-enabling the interrupt system after the inseparable instruction sequence. Interrupt Class Management An interrupt class covers a set of interrupt sources with the same importance, i.e. the same priority from the system's viewpoint. Interrupts of the same class must not interrupt each other. M2 supports this function with two features: Users Manual 5 - 20 2000-06-15 SDA 6000 Interrupt and Trap Functions Classes with up to 4 members can be established by using the same interrupt priority (ILVL) and assigning a dedicated group level (GLVL) to each member. This functionality is built-in and handled automatically by the interrupt controller. Classes with more than 4 members can be established by using a number of adjacent interrupt priorities (ILVL) and the respective group levels (4 per ILVL). Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class. All requests from the same or any lower level are blocked now, i.e. no request of this class will be accepted. The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities, depending on the number of members in a class. A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8, which is the highest priority (ILVL) in class 2. Class 1 requests or PEC requests are still serviced in this case. The 24 interrupt sources (excluding PEC requests) are assigned to 3 classes of priority rather than to 7 different levels, as the hardware support would do. Table 5-5 ILVL (Priority 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No service! X X X X X X X X Interrupt Class 3 5 sources on 2 levels X X X X X X Interrupt Class 2 9 sources on 3 levels X X X X X Interrupt Class 1 5 sources on 2 levels Software controlled Interrupt Classes (Example) GLVL 3 2 1 0 PEC service on up to 8 channels Interpretation Users Manual 5 - 21 2000-06-15 SDA 6000 Interrupt and Trap Functions 5.2.2 Saving the Status during Interrupt Service Before an interrupt request that has been arbitrated is actually serviced, the status of the current task is automatically saved on the system stack. The CPU status (PSW) is saved along with the location, where the execution of the interrupted task is resumed after returning from the service routine. This return location is specified through the Instruction Pointer (IP) and, in case of a segmented memory model, the Code Segment Pointer (CSP). Bit SGTDIS in register SYSCON controls how the return location is stored. The system stack first receives the PSW, followed by the IP (unsegmented) or the CSP and then IP (segmented mode). This optimizes the usage of the system stack, if segmentation is disabled. The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that is to be serviced, so the CPU now executes on the new level. If multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to `1'. In this case the return location that is saved on the stack is not the next instruction in the instruction flow, but rather the multiply or divide instruction itself, as this instruction has been interrupted and will be completed after returning from the service routine. Figure 5-3 Task Status Saved on the System Stack The interrupt request flag of the source that is being serviced is cleared. The IP is loaded with the vector associated with the requesting source (the CSP is cleared in case of segmentation) and the first instruction of the service routine is fetched from the respective vector location, which is expected to branch to the service routine itself. The data page pointers and the context pointer are not affected. Users Manual 5 - 22 2000-06-15 SDA 6000 Interrupt and Trap Functions When the interrupt service routine is left (RETI is executed), the status information is popped from the system stack in reverse order, taking into account the value of bit SGTDIS. Context Switching An interrupt service routine usually saves all the registers it uses on the stack, and restores them before returning. The more registers a routine uses, the more time is wasted with saving and restoring. The M2 allows the complete bank of CPU registers (GPRs) to switch with a single instruction, so the service routine executes within its own, separate context. The instruction "SCXT CP, #New_Bank" pushes the contents of the context pointer (CP) on the system stack and loads CP with the immediate value "New_Bank", which selects a new register bank. The service routine may now use its "own registers". This register bank is preserved when the service routine terminates, i.e. its contents are available on the next call. Before returning (RETI) the previous CP is simply POPped from the system stack, which returns the registers to the original bank. Note: The first instruction following the SCXT instruction must not use a GPR. Resources that are used by the interrupting program must eventually be saved and restored, e.g. the DPPs and the registers of the MUL/DIV unit. 5.2.3 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction (I1) is fetched from the interrupt vector location. The basic interrupt response time for the M2 is 3 instruction cycles. Pipeline Stage FETCH DECODE EXECUTE WRITEBACK Cycle 1 N N-1 N-2 N-3 Cycle 2 N+1 N N-1 N-2 Cycle 3 N+2 TRAP (1) N N-1 Cycle 4 I1 TRAP (2) TRAP N Interrupt Response Time IR-Flag 1 0 UED11129 Figure 5-4 Users Manual Pipeline Diagram for Interrupt Response Time 5 - 23 2000-06-15 SDA 6000 Interrupt and Trap Functions All instructions in the pipeline, including instruction N (during which the interrupt request flag is set), are completed before entering the service routine. The actual execution time for these instructions (e.g. wait-states) therefore influences the interrupt response time. In Figure 5-4 the respective interrupt request flag is set in cycle 1 (the fetching of instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline, replacing instruction N+1 and clearing the source's interrupt request flag to `0'. Cycle 4 completes the injected TRAP instruction (save PSW, IP and CSP, if in segmented mode) and fetches the first instruction (I1) from the respective vector location. All instructions that entered the pipeline, after the setting of the interrupt request flag (N+1, N+2), will be executed after returning from the interrupt service routine. The minimum interrupt response time is 5 states (10 TCL). This requires program execution from the internal code memory, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum interrupt response time under these conditions is 6 state times (12 TCL). The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine (including N). * When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, or when instruction N explicitly writes to the PSW or the SP, the minimum interrupt response time may be extended by 1 state time for each of these conditions. * When instruction N reads an operand from the internal code memory, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum interrupt response time may be extended by 2 state times during internal code memory program execution. * In case instruction N reads the PSW and instruction N-1 effects the condition flags, the interrupt response time may be extended by 2 state times. The worst case interrupt response time during internal code memory program execution adds 12 state times (24 TCL). Any reference to external locations increases the interrupt response time due to pipeline related access priorities. The following conditions have to be considered: * Instruction fetch from an external location * Operand read from an external location * Result write-back to an external location There are a number of combinations depending on where the instructions, source and destination operands are located. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: * The worst case interrupt response time, including external accesses, will occur when instructions N, N+1 and N+2 are executed out of external memory, instructions N-1 Users Manual 5 - 24 2000-06-15 SDA 6000 Interrupt and Trap Functions and N require external operand read accesses, instructions N-3 through N write back external operands, and the interrupt vector also points to an external location. In this case the interrupt response time is the time needed to perform 9 word bus accesses, because instruction I1 cannot be fetched via the external bus until all write, fetch and read requests from preceding instructions in the pipeline are terminated. * When the interrupt vector, of the example above, is pointing into the internal code memory, the interrupt response time is 7 word bus accesses plus 2 states because the fetching of instruction I1 from internal code memory can start earlier. * When instructions N, N+1 and N+2 are executed out of the external memory and the interrupt vector points to an external location, but all operands for instructions N-3 through N are in internal memory, then the interrupt response time is the time needed to perform 3 word bus accesses. * When the interrupt vector, of the example above, is pointing into the internal code memory, the interrupt response time is 1 word bus access plus 4 states. After an interrupt service routine has been terminated by executing the RETI instruction, and if further interrupts are pending, the next interrupt service routine will not be entered until at least two instruction cycles of the program that was interrupted have been executed. In most cases two instructions will be executed during this time. Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction (without cache hit), if it reads an operand from internal code memory, or if it is executed out of the internal RAM. Note: A bus access, in this context, includes all delays which can occur during an external bus cycle. 5.2.4 PEC Response Times The PEC response time defines the time between an interrupt request flag of an enabled interrupt source being set and the PEC data transfer being started. The basic PEC response time for the M2 is 2 instruction cycles. Users Manual 5 - 25 2000-06-15 SDA 6000 Interrupt and Trap Functions Pipeline Stage FETCH DECODE EXECUTE WRITEBACK Cycle 1 N N-1 N-2 N-3 Cycle 2 N+1 N N-1 N-2 Cycle 3 N+2 PEC N N-1 Cycle 4 N+2 N+1 PEC N PEC Response Time IR-Flag 1 0 UED11130 Figure 5-5 Pipeline Diagram for PEC Response Time In Figure 5-5, the respective interrupt request flag is set in cycle 1 (fetching instruction N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC transfer "instruction" is imported into the decode stage of the pipeline, suspending instruction N+1 and clearing the source's interrupt request flag to `0'. Cycle 4 completes the imported PEC transfer and resumes the execution of instruction N+1. All instructions that entered the pipeline after setting of the interrupt request flag (N+1, N+2) will be executed after the PEC data transfer. Note: When instruction N reads any of the PEC control registers PECC7 ... PECC0, while a PEC request wins the current round of prioritization, the round is repeated and the PEC data transfer is started one cycle later. The minimum PEC response time is 3 states (6 TCL). This requires program execution from the internal code memory, no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle. When the interrupt request flag is set during the first state of an instruction cycle, the minimum PEC response time under these conditions is 4 state times (8 TCL). The PEC response time is increased by all delays of the instructions in the pipeline which are executed before starting the data transfer (including N). * When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the minimum PEC response time may be extended by 1 state time for each of these conditions. * When instruction N reads an operand from the internal code memory, or when N is a call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response time may be extended by 2 state times during internal code memory program execution. Users Manual 5 - 26 2000-06-15 SDA 6000 Interrupt and Trap Functions * If instruction N reads the PSW and instruction N-1 effects the condition flags, the PEC response time may additionally be extended by 2 state times. The worst case PEC response time during internal code memory program execution adds to 9 state times (18 TCL). Any reference to external locations increases the PEC response time due to pipeline related access priorities. The following conditions have to be considered: * Instruction fetch from an external location * Operand read from an external location * Result write-back to an external location There are a number of combinations depending on where the instructions, source and destination operands are located. Note, however, that only access conflicts contribute to the delay. A few examples illustrate these delays: * The worst case interrupt response time, including external accesses, will occur when instructions N and N+1 are executed out of external memory, instructions N-1 and N require external operand read accesses and instructions N-3, N-2 and N-1 write back external operands. In this case the PEC response time is the time needed to perform 7 word bus accesses. * When instructions N and N+1 are executed out of the external memory, but all operands for instructions N-3 through N-1 are in internal memory, then the PEC response time is the time needed to perform 1 word bus access plus 2 state times. Once a request for PEC service has been acknowledged by the CPU, the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal code memory or external memory and to write the destination operand over the external bus in an external program environment. Note: A bus access, in this context, includes all delays which can occur during an external bus cycle. For an EPEC request, the basic response time is 3 instruction cycles. The minimum response time is reached when the request occurs at the end of an instruction cycle. In this case the response time is 5 states (10 TCL). All the conditions described below that may increase the response time apply to the EPEC. 5.2.5 Fast Interrupts The interrupt inputs are sampled every 8 states (16 TCL), i.e. external events are scanned and detected in timeframes of 16 TCL. M2 provides 8 interrupt inputs that are sampled every 2 TCL, so external events are captured faster than with standard interrupt inputs. Users Manual 5 - 27 2000-06-15 SDA 6000 Interrupt and Trap Functions The 8 lines can be programmed individually to this fast interrupt mode, where the trigger transition (rising, falling or both) can also be selected. The External Interrupt Control register EXICON controls this feature for all 8 signals. EXICON (F1C0H / E0H) 15 14 13 12 11 10 9 8 7 6 5 4 EXI7ES rw EXI6ES rw EXI5ES rw EXI4ES rw EXI3ES rw EXI2ES rw Reset Value: 0000H 3 2 1 0 EXI1ES rw EXI0ES rw Bit EXIxES Function External Interrupt x Edge Selection Field (x = 7 ... 0) 0 0: Fast external interrupts disabled: standard mode 0 1: Interrupt on positive edge (rising) 1 0: Interrupt on negative edge (falling) 1 1: Interrupt on any edge (rising or falling) Note: The fast external interrupt inputs are sampled every 2 TCL. The interrupt request arbitration and processing, however, is executed every 8 TCL. In Sleep mode, no clock is available for sampling, but interrupt request detection is still possible on fast interrupt request lines using asynchronous logic. 5.3 Trap Functions Traps interrupt the current execution similar to standard interrupts. However, trap functions offer the possibility to bypass the interrupt system's prioritization process in cases where immediate system reaction is required. Trap functions are not maskable and always have priority over interrupt requests on any priority level. M2 provides two different kinds of trapping mechanisms. Hardware traps are triggered by events that occur during program execution (e.g. illegal access or undefined opcode), software traps are initiated via an instruction within the current execution flow. Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine. The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00'0000H through 00'01FCH will be branched. Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and a jump is taken to the specified vector location. When segmentation is enabled and a trap is executed, the CSP for the trap service routine is set to code segment 0. No Interrupt Request flags are affected by the TRAP instruction. The Users Manual 5 - 28 2000-06-15 SDA 6000 Interrupt and Trap Functions interrupt service routine called by a TRAP instruction must be terminated with a RETI (return from interrupt) instruction to ensure correct operation. Note: The CPU level in register PSW is not modified by the TRAP instruction, so the service routine is executed on the same priority level from which it was invoked. Therefore, the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts, other than when triggered by a hardware trap. Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program (not identified at assembly time). A hardware trap may also be triggered intentionally, e.g. to emulate additional instructions by generating an Illegal Opcode trap or to enter the OCDS Software Debug Mode. M2 distinguishes eight different hardware trap functions. When a hardware trap condition has been detected, the CPU branches to the trap vector location for the respective trap condition. Depending on the trap condition, the instruction which caused the trap is either completed or cancelled (i.e. it has no effect on the system state) before the trap handling routine is entered. Hardware traps are non-maskable and always have priority over every other CPU activity. If several hardware trap conditions are detected within the same instruction cycle, the highest priority trap is serviced (see Table 5-1). PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and the CPU level in the PSW register is set to the highest possible priority level (i.e. level 15), disabling all interrupts. The CSP is set to code segment zero, if segmentation is enabled. A trap service routine must be terminated with the RETI instruction. The nine hardware trap functions of M2 are divided into two classes: Class A traps are * external Non-Maskable Interrupt (NMI) * Stack Overflow * Stack Underflow trap These traps share the same trap priority, but have an individual vector address. Class B traps are * * * * * Undefined Opcode Protection Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap These traps share the same trap priority and vector address. The Debug Trap (see chapter x "OCDS") is set apart and has its own individual priority and vector address. Users Manual 5 - 29 2000-06-15 SDA 6000 Interrupt and Trap Functions The bit-addressable Trap Flag Register (TFR) allows a trap service routine to identify the kind of trap which caused the exception. Each trap function is indicated by a separate request flag. When a hardware trap occurs, the corresponding request flag in the TFR register is set to `1'. TFR 15 - Reset Value: 0000H 14 STK OF 13 STK UF 12 DE BUG 11 - 10 - 9 - 8 - 7 UND OPC 6 - 5 - 4 - 3 PRT FLT 2 ILL OPA 1 ILL INA 0 ILL BUS rw rw rw rw - - - - rw - - - rw rw rw rw Bit ILLBUS ILLINA ILLOPA Function Illegal External Bus Access Flag An external access has been attempted without a defined external bus. Illegal Instruction Access Flag A branch to an odd address has been attempted. Illegal Word Operand Access Flag A word operand access (read or write) to an odd address has been attempted. Protection Fault Flag A protected instruction with an illegal format has been detected. Undefined Opcode Flag The currently decoded instruction has no valid M2 opcode. Debug Trap Flag A debug event programmed to trigger a Debug Trap has been detected by the OCDS. Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN. Stack Overflow Flag The current stack pointer value falls below the content of register STKOV. PRTFLT UNDOPC DEBUG STKUF STKOF Note: The trap service routine must clear the respective trap flag, otherwise a new trap will be requested after exiting the service routine. Setting a trap request flag by software causes the same effects as if it had been set by hardware. The reset functions (hardware, software, watchdog) may be regarded as a type of trap. Reset functions have the highest system priority (trap priority IV). The Debug Trap has the second highest priority (trap priority III) and can interrupt any class A or class B trap. If a class A or class B trap and a Debug Trap occur at the same time, both flags are set in the TFR but the Debug Trap is executed first. Users Manual 5 - 30 2000-06-15 SDA 6000 Interrupt and Trap Functions Class A traps have the third highest priority (trap priority II), class B traps are on the 4rd rank so a class A trap can interrupt a class B trap. If more than one class A trap occurs at a time, they are prioritized internally, with the NMI trap on the highest and the stack underflow trap on the lowest priority. All class B traps have the same trap priority (trap priority I). When several class B traps are activated at a time, the corresponding flags in the TFR register are set and the trap service routine is entered. Since all class B traps have the same vector, the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine. A class A trap occurring during the execution of a class B trap service routine will be serviced immediately. However, during the execution of a class A trap service routine, any class B trap which occurs will not be serviced until the class A trap service routine is exited with a RETI instruction. In this case, the occurrence of the class B trap condition is stored in the TFR register, but the IP value of the instruction which caused this trap is lost. In the case where e.g. an Undefined Opcode trap (class B) occurs simultaneously with an NMI trap (class A), both the NMI and the UNDOPC flag is set, the IP of the instruction with the undefined opcode is pushed onto the system stack, but the NMI trap is executed. After returning from the NMI service routine, the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap. Debug Trap The OCDS may be programmed to trigger a Debug Trap when a debug event (match of data/address comparison, execution of DEBUG instruction, event on brk_in_n input) rises. This is normally used to call a monitor routine (software debug mode) for debugging purposes. Normal program execution resumes when a regular RETI instruction is executed, which ends the monitor routine. This trap has the highest priority (except for reset functions) but the monitor routine can reduce its own priority by writing the ILVL field in the PSW. External NMI Trap Whenever a high to low transition on the designated nmi_n pin (Non-Maskable Interrupt) is detected, the NMI flag in the TFR register is set and the CPU will enter the NMI trap routine. The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap. Note: The nmi_n pin is sampled with every CPU clock cycle to detect transitions. Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV, the STKOF flag in the TFR register is set and the CPU Users Manual 5 - 31 2000-06-15 SDA 6000 Interrupt and Trap Functions will enter the stack overflow trap routine. Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP. When an implicit decrement of the SP is made through a PUSH or CALL instruction, or upon interrupt or trap entry, the IP value pushed is the address of the following instruction. When the SP is decremented by a subtract instruction, the IP value pushed represents the instruction address following the post subtract-instruction command. To recover from stack overflow it must be ensured that there is enough excess space on the stack to save the current system state twice (PSW, IP, in segmented mode also CSP). Otherwise, a system reset should be generated. Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN, the STKUF flag is set in the TFR register and the CPU will enter the stack underflow trap routine. Again, which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP. When an implicit increment of the SP is made through a POP or return instruction, the IP value pushed is the address of the following instruction. When the SP is incremented by an add instruction, the pushed IP value represents the instruction address following the post add-instruction command. Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid M2 opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The IP value pushed onto the system stack is the address of the instruction that caused the trap. This can be used to emulate unimplemented instructions. The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP. In order to resume processing, the stacked IP value must be incremented by the size of the undefined instruction, which is determined by the user, before a RETI instruction is executed. Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction, and the byte following the opcode is not the complement of the opcode, the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine. The protected instructions include DISWDT, EINIT, IDLE, PWRDN, SRST, and SRVWDT. The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap. Users Manual 5 - 32 2000-06-15 SDA 6000 Interrupt and Trap Functions Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address, the ILLOPA flag in the TFR register is set and the CPU enters the illegal word operand access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. Illegal Instruction Access Trap Whenever a branch is made to an odd byte address, the ILLINA flag in the TFR register is set, and the CPU enters the illegal instruction access trap routine. The IP value pushed onto the system stack is the illegal odd target address of the branch instruction. Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch, data read or data write, and no external bus configuration has been specified, the ILLBUS flag in the TFR register is set, and the CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap. 5.3.1 External Interrupt Source Control Fast external interrupts may also have interrupt sources selected from other peripherals. This function is very advantageous in Slow Down or in Sleep mode if, for example, the A/D converter input shall be used to wakeup the system. The register EXISEL is used to switch alternate interrupt sources to the interrupt controller. The EXISEL register is defined as follows: Users Manual 5 - 33 2000-06-15 SDA 6000 Interrupt and Trap Functions EXISEL 15 14 EXI7SS 13 12 11 10 9 8 EXI4SS 7 6 EXI3SS 5 4 EXI2SS ResetValue:0000H 3 2 1 0 EXI1SS EXI0SS EXI6SS EXI5SS rw Bit EXIxSS rw Function rw rw rw rw rw rw External Interrupt x Source Selection Field (x = 7 ... 0) 0 0: Input from default pin 0 1: Input from "alternate source" 1 0: Input from default pin ORed with "alternate source" 1 1: Input from default pin ANDed with "alternate source" Alternate Source (input FEIxIN_B) ADWINT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Fast Interrupt 0 1 2 3 4 5 6 7 Users Manual 5 - 34 2000-06-15 System Control & Configuration SDA 6000 System Control & Configuration 6 System Control & Configuration M2 has extended features for system level control and configuration. Most of these features are now handled by a new block inside the M2 which is the System Control Unit (SCU). The SCU is used to control system-level tasks such as reset control, clock control and power management. It is implemented to ease compatibility of new M2 based products with already existing C16x derivatives. M2 provides the following functions for system control and configuration: * * * * * * * System and Controller Core reset function System and Controller Core start-up configuration Configuration Registers protection Clock Management functions Power Management modes (Idle, Sleep, Power Down) Watchdog timer Identification registers for Core (CPU, SCU, OCDS) and system (manufacturer, chip version, memory) identification These functions are explained in further details in the following paragraphs. 6.1 System Reset The internal system reset function provides the initialization of the M2 into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN (Hardware Reset Input), upon the execution of the SRST instruction (Software Reset) or by an overflow of the watchdog timer. Whenever one of these conditions occurs, the CBC is reset into its predefined default state through an internal reset procedure. When a reset, other than a watchdog reset, is initiated, pending internal hold states are cancelled and any external bus cycle is aborted (see description). After the reset condition is removed, M2 will start program execution from memory location 00'0000H in code segment zero. This start location will typically hold a branch instruction to the start of a software initialization routine for the configuration of peripherals and M2 SFRs. M2 recognizes the following reset conditions. Reset Type Power-on Reset Short Hardware Reset Long Hardware Reset Watchdog Timer Reset Software Reset Users Manual Short-cut PONR SHWR LHWR WDTR SWR 6-3 Condition Power-on 16 TCL < tRSTIN 2048 TCL tRSTIN > 2048 TCL WDT overflow SRST command 2000-06-15 SDA 6000 System Control & Configuration Reset conditions are indicated in the WDTCON register. Hardware Reset A hardware reset is triggered asynchronously by a falling edge of the reset input signal, RSTIN. To ensure the recognition of the RSTIN signal, it must be held low for at least 2 CPU clock cycles, assuming the clock input signal is stable. Also, shorter RSTIN pulses may trigger a hardware reset, however, this is not recommended. The internal reset condition is prolonged until one of the following conditions arises: * the rising edge of the RSTIN signal, or * the termination of the reset sequence, if RSTIN was deasserted before, or * the termination of the lengthening conditions. After termination of the reset state, program execution will start. Three different kinds of hardware reset conditions are considered: * Power-on Reset A complete power-on reset requires an active RSTIN time until a stable clock signal is available. The on-chip oscillator needs about 2 ms to stabilize. * Long Hardware Reset A long hardware reset requires an RSTIN active time longer than the duration of the internal reset sequence. The duration of the internal reset sequence is 2056 TCL. After the internal reset sequence has been completed, the RSTIN input is sampled. As long as the reset input is still active the internal reset condition is prolonged. Accordingly, the internal hardware reset (HWRST) is active until the external reset on the RSTIN input becomes inactive. Note: The hardware reset is also used as a wake up from power down state; in this case the internal system reset will be lengthened (execution of 1. instruction delayed) until the oscillator and PLL have been stabilized. * Short Hardware Reset The RSTIN active time of a short hardware reset is between 16 TCL and 2056 TCL. If the RSTIN signal is active for at least 16 TCL clock cycles the internal reset sequence is started (see below). In case of a short HW-reset, the internal HWRST signal is prolonged until the reset sequence is finished. Software Reset The reset sequence can be triggered at any time via the protected instruction SRST (Software Reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or upon a hardware trap that reveals a system failure. Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. Other than Users Manual 6-4 2000-06-15 SDA 6000 System Control & Configuration hardware and software reset the watchdog reset completes a running external bus or XBus cycle. 6.1.1 Behavior of I/Os during Reset During the internal reset sequence all of the M2's I/O pins are configured as inputs by clearing the associated direction registers and switching their pin drivers to the high impedance state. This ensures that the M2 and external devices will not try to drive the same pin to different levels. Outputs are generally driven to their expected inactive state during reset. Output pins driven to `0' are: A13 ... A0; MEMCLK, CLKEN, XTAL2, COR, BLANK and TDO. Output pins driven to `1' are: A15 (CAS),A14 (RAS), RD, CSROM, CSDRAM, WR, P4.5(CS3), P4.4 ... P4.0, LDQM and UDQM. 6.1.2 Reset Values for the Controller Core Registers During the reset sequence the registers of the C166 CBC are preset with a default value. Most C166 CBC SFRs are cleared to zero, so the interrupt system is off after reset. A few exceptions to this rule provide a first pre-initialization, which is either fixed or controlled by input pins. DPP1: DPP2: DPP3: CP: STKUN: STKOV: SP: SYSCON: BUSCON0: ONES: 0001H (points to data page 1) 0002H (points to data page 2) 0003H (points to data page 3) FC00H FC00H FA00H FC00H 0400H (set according to start-up configuration) 15B7H (set according to start-up configuration) FFFFH (fixed value) 6.1.3 The Internal RAM after Reset The contents of the internal RAM are not affected by a reset. However, after a power-on reset, the contents of the internal RAM are undefined. This implies that the GPRs (R15 ... R0) and the PEC source and destination pointers (SRCP7 ... SRCP0, DSTP7 ... DSTP0), which are mapped into the internal RAM, are also unchanged after a warm reset, software reset or watchdog reset, but are undefined after a power-on reset. 6.2 System Start-up Configuration Although most of the programmable features of the M2 are either selected during the initialization routine or repeatedly during program execution, there are some features Users Manual 6-5 2000-06-15 SDA 6000 System Control & Configuration that must be selected earlier, because they are used for the first access of the program execution. The system start-up configuration is determined by the level on PORT4 at the end of the internal reset sequence. During reset internal pull-up devices are active on PORT4 lines, so their input level is high, if the respective pin is left open, or is low, if the respective pin is connected to an external pull-down device. The value FFFFH on PORT4 will select the default configuration during reset. If a particular configuration is required, the corresponding line(s) should be driven low according to the coding of the selections, as shown below. Registers SYSCON and BUSCON0 are initialized according to the selected configuration. Pins that control the operation of the internal control logic and reserved pins are evaluated only during a hardware triggered reset sequence. Pins that influence the configuration of the M2 are evaluated during any reset sequence, e.g. also during software and watchdog timer triggered resets. The configuration input via PORT4 is latched in register RP0H for subsequent evaluation by software. RP0H 15 0 Reset Value: 00XXH 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 1 5 4 3 2 1 1 CS ENA 0 1 SALSEL(2..0) r Bit CSENA Function Chip Select Lines Selection Number of external ROMs. Description of possible selections: see table below (Start up Configuration) Segment Address Lines Selection Number of active segment address outputs. Description of possible selections: see table below (Start up Configuration) SALSEL (2 ... 0) Bootstrap Loader Mode Pin P4.0 (BSL) activates the on-chip bootstrap loader, when low, during reset. The bootstrap loader allows the start code to move into the internal RAM of the M2 via the serial interface ASC0. The M2 will remain in bootstrap loader mode until a hardware reset with P4.0 high or a software reset. Default: The M2 starts fetching code from location 00'0000H, the bootstrap loader is off. Users Manual 6-6 2000-06-15 SDA 6000 System Control & Configuration Chip Select Line Pin P4.1 (CSENA) defines the external memory configuration. When pulled low it enables chip select 3 (CS3) (a second ROM device is assumed). RP0H.1 = `0' denotes the memory configuration with only one ROM device while RP0H.1 = `1' indicates availability of the 2nd ROM device. Note: CS3 status cannot be changed via software after reset. Segment Address Lines The status of Pins P4.5 ... P4.3 (SALSEL) during reset defines the number of active segment address lines. This allows the selection which pins of Port 4 drive address lines and which are used for general purpose I/O. The three bits are latched in register RP0H. Depending on the system architecture the required address space is chosen and accessible right from the start, so the initialization routine can directly access all locations without prior programming. The required pins of Port 4 are automatically switched to address output mode. During runtime the configured number of segment address line can be read from bit field RP0H.5 (= SALSEL.2) ... RP0H.3 (= SALSEL.0). SALSEL 111 110 101 100 011 010 001 000 Segment Address Lines A20, A19, A18, A17, A16 A19, A18, A17, A16 A18, A17, A16 A17, A16 A16 - - - Directly Accessible Address Space 4 MByte (Default without pull-downs) 2 MByte 1 MByte 512 KByte 256 KByte 128 KByte 128 KByte 128 KByte Default: 5-bit segment address (A20 ... A16) allowing access to 4 MByte. Note: The selected number of segment address lines cannot be changed via software after reset. Users Manual 6-7 2000-06-15 SDA 6000 System Control & Configuration 6.3 Register Write Protection The System Control Unit (SCU) provides two different protection types of configuration registers: * Unprotected Registers * Protectable Registers The unprotected registers allow the reading and writing (if not read-only) of register values without any restrictions. However, the write access of the protectable registers (security registers) can be programmed for three different modes of security level, whereas the read access is always unprotected: * Write Protected Mode * Low Protected Mode * Unprotected Mode In write protected mode, the registers can not be accessed by a write command. However, in low protected mode, the registers can be written with a special command sequence (see description below). If the registers are set to unprotected mode, all write accesses are possible. Some register controlled functions and modes which are critical for M2's operation are locked after the execution of EINIT, so these vital system functions cannot be changed inadvertently e.g. by software errors. However, as these security registers also control the power management, they need to be accessed during operation to select the appropriate mode. The switching between the different security levels is controlled by a state machine. By using a password and command sequence the security levels can be changed. After reset the unprotected mode is always automatically selected. The EINIT command switches the security level automatically to protected mode. The low protected mode is especially important for a standby state of the application. This mode allows fast accesses within 2 commands to the protected registers without removing the protection completely. Security Level Switching Two registers are provided for switching the security level, the security level command register SCUSLC and the security level status register SCUSLS. The security level command register SCUSLC is used to control the state machine for switching the security level. The SCUSLC register is loaded with the different commands of the command sequence necessary to control a change in the security level. It is also used for the one unlock command, which is necessary in the low protected mode to access one protected register. The commands of the (unlock) command sequence are characterized by certain pattern words (such as AAAAH) or by patterns combined with an 8-bit password. For command definition see the following state diagram (Figure 6-1). Users Manual 6-8 2000-06-15 SDA 6000 System Control & Configuration The new password is defined with command 3 and stored in the according 8-bit field in the SCUSLS register. The SCUSLC register is defined as follows SCUSLC 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 COMMAND rw Bit Command Function Code of Command to be Executed Command 0: `AAAAH' Command 1: `5554H' Command 2: `96 & inverse password' Command 3: `000b' & new level & `000b' & new password Command 4: `8EH' & inverse password (Command 4 unlocks protected registers for one write access if current security level is in low protected mode.) The security level status register SCUSLS is a read only register which shows the current password, the actual security level and the state of the switching state machine. The SCUSLS is defined as follows: Users Manual 6-9 2000-06-15 SDA 6000 System Control & Configuration SCUSLS 15 14 STATE Reset Value: 0000H 13 12 SL 11 10 - 9 - 8 - 7 6 5 4 3 2 1 0 PASSWORD r r r Bit SL Function Current Security Level `00': Unprotected Write Mode `01': Low Protected Mode `10': Reserved `11': Write Protected Mode Current State `000': State 0 = Wait for Command 0. `001': State 1 = Wait for Command 1. `010': State 2 = Wait for Command 2. `011': State 3 = Wait for new security level and new password (Command 3). `100': State 4 = Protected registers are unlocked. Write access to one register is possible (only in low protected mode). `101': Reserved `110': Reserved `111': Reserved PASSWORD Current Password STATE The following registers are defined as protected (security) registers: * SYSCON1 * SYSCON2 * SYSCON3 Users Manual 6 - 10 2000-06-15 SDA 6000 System Control & Configuration The following state diagram shows the state machine for security level switching and for unlock command execution in low protected mode: Command 3 1) or any other SCU Register Write Access Reset State 0 State 3 Command 0 Command 1 or any other SCU Register Write Access Any SCU Register Write Access State 4 State 1 Command 1 State 2 UED11131 Figure 6-1 State Machine for Security Level Switching Note: 1) The new security level and password are valid, only if the security level command register is accessed. c_SCU is an abbreviation for "write access to any SCU register", i.e. write access to any of the following registers: SYSCON1, SYSCON2, SCUSLC, SCUSLS, RP0H, XPERCON, WDT, WDTCON, EXICON, EXISEL, ISNC, FOCON, SYSCON3 Note: The FOCON and SYSCON3 registers do not provide any function within the M2. Nevertheless they are implemented in the system control unit of the embedded microcontroller and write access to the associated addresses will influence the state machine for security level switching. Write Access in Low Protected Mode The write access in low protected mode is also done via a command sequence. First the specific command 4 (see Figure 6-1) has to be written to register SCUSLC with the current password. After this command, all security registers are unlocked until the next write access to any SCU register is done. Read access is always possible to all registers of the SCU and will not influence the command sequences. In register SCUSCS the actual status of the command state machine can always be read. It is recommended to use an atomic sequence for all command sequences. Users Manual 6 - 11 2000-06-15 Command 2 Command 4 and Low Protected Mode Command 2 or any other SCU Register Write Access SDA 6000 System Control & Configuration 6.4 Power Reduction Modes Three power reduction modes with different levels of power reduction, which may be entered under software control, have been implemented in M2: Idle Mode: The CPU is stopped, while the peripherals including watchdog timer continue their operation at low clock frequency. Sleep Mode: CPU, peripherals and PLL are completely turned off. The controller ADC operates in wake-up mode. The real-time-clock is still in operation. Power Down Mode: All modules are turned off. Mode Oscillator PLL CPU CADC RTC Peripherals Bus Interface 1) 2) 3) Normal on on 33 MHz 33 MHz1) 3 MHz 33 MHz 100/66 MHz3) Idle on on 3 MHz/ stopped 3 MHz2) 3 MHz 3 MHz off Sleep on off no clock/ stopped 3 MHz2) 3 MHz off off Power Down off off no clock/ stopped off off off off Conversion mode Wake up mode Depending on value of CLKCON (see Chapter 8) In the table above clocking frequencies have been specified, indicating that power reduction is achieved by means of clock-gating. None of the power supplies are internally switched, neither may voltage be turned off at the supply pins. M2's power management functions are supplemented by a Real Time Clock (RTC) timer with optional periodic wake-up from idle mode. The periodic wake-up combines the reduced power consumption in power reduction modes with a high level of system availability. External signals and events can be scanned (at a lower rate) by periodically activating the CPU and selected peripherals which then return to power-save mode after a short time. This greatly reduces the system's average power consumption. Entering and Terminating Idle and Sleep Mode All three modes are entered by writing register SLEEPCON (see register definition below) and issuing the IDLE instruction. All external bus actions are completed before entry to Idle, Sleep or Power Down mode. Normal operation is resumed after Idle mode upon any interrupt request. To return from Sleep mode, external, wake up- or RTCUsers Manual 6 - 12 2000-06-15 SDA 6000 System Control & Configuration interrupt requests can be used. Power down mode can only be terminated with hardware reset. To prevent unintentional entry into Idle mode, the IDLE instruction has been implemented as a protected 32-bit instruction. Mode Entry by ... Exit by ... Idle any interrupt request Sleep external, wake up- or RTCIRQ Power Down HW-reset writing SLEEPCON and issuing IDLE instruction Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered, regardless of bit IEN. For a request selected for CPU interrupt service, the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled. After the RETI (Return from Interrupt) instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction. Otherwise, if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction. For a request which was programmed for PEC service, a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled. After the PEC data transfer has been completed the CPU remains in Idle mode. Otherwise, if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system, the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction. Users Manual 6 - 13 2000-06-15 SDA 6000 System Control & Configuration Denied CPU Interrupt Request Accepted Active Mode IDLE Instruction Idle Mode Denied PEC Request Executed PEC Request UED11132 Figure 6-2 Transitions between Idle Mode and Active Mode Any interrupt request, whose individual Interrupt Enable flag was set before Idle mode was entered, will terminate Idle mode regardless of the current CPU priority. The CPU will not go back into Idle mode when a CPU interrupt request is detected, even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system (IEN = `0'). The CPU will only go back into Idle mode when the interrupt system is globally enabled (IEN = `1') and a PEC service on a priority level higher than the current CPU level is requested and executed. Note: An interrupt request which is individually enabled and assigned to priority level 0 will terminate Idle mode. However, the associated interrupt vector will not be accessed. The watchdog timer may be used to monitor the Idle mode: an internal reset will be generated if no interrupt request occurs before the watchdog timer overflows. To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered. Power Down Mode Clocking of all internal blocks is stopped in Power Down Mode, the contents of the internal RAMs, however, are preserved through the voltage supplied via the VDD pins. The watchdog timer is stopped in Power Down Mode. This mode can only be terminated by an external hardware reset, e.g. by asserting a low level on the RSTIN pin. This reset will initialize all SFRs and ports to their default state, but will not change the contents of the internal RAMs. SDRAM Refreshing Before entering into one of the power save modes the external SDRAM must be put into self-refresh-mode by use of register EBIDIR (see Chapter 4.5). Users Manual 6 - 14 2000-06-15 SDA 6000 System Control & Configuration Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU is stopped, while all peripherals continue their operation in the same way previously described. Therefore all ports pins, which are configured as general purpose output pins, output the last data value which was written to their port output latches. If the alternate output function of a port pin is used by a peripheral, the state of the pin is determined by the operation of the peripheral. Port 4 outputs the segment address for the last access on the pins that were selected during reset, otherwise the output pins of Port 4 represent the port latch data. During Power Down mode the oscillator and the clocks to the CPU and peripherals are turned off. Like in idle mode, all port pins, which are configured as general purpose output pins, output the last data value which was written to their port output latches. When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off. SYSCON1 15 - Reset Value: 0001H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 0 SLEEPCON rw Bit SLEEPCON Function Power Save Mode Selection 00: Idle Mode 01: Sleep Mode 10: reserved 11: Power Down Mode Note: This register is a protected register; it's security level is automatically set to full write protection after execution of the EINIT instruction. 6.5 Dedicated Pins M2 has different dedicated Pins than other controllers of C16X family. The following dedicated pins are not available: ALE, READY, EA, NMI. The following table explains M2 specific dedicated pins. The external read strobe RD controls the output drivers of external memory or peripherals when M2 reads data from these external devices. During reset an internal pull-up ensures an inactive (high) level on the RD output. Users Manual 6 - 15 2000-06-15 SDA 6000 System Control & Configuration Pin(s) RD WR LDQM, UDQM XTAL1, XTAL2 RSTIN CSDRAM, CSROM, CS3 MEMCLK, CLKEN CVBS1, CVBS2 R, G, B CORBLA HSYNC, VSYNC Function External Read Strobe Write Enable Strobe for SDRAM Byte Mask Signals for SDRAM Oscillator Input/Output Reset Input Pin Chip Select Signals Clock Signals for SDRAM CVBS Input Signals Analog RGB Output Contrast Reduction and Blanking Pin Sync Inputs/Outputs for the Display The external write strobe WR controls the data transfer from the M2 to an external memory. During reset an internal pull-up ensures an inactive (high) level on the WR output. Byte mask signals LDQM and UDQM control the byte access to an external SDRAM according to the PC100 specification. These pins are active if either the high byte or the low byte of a 16-bit word are written. The oscillator input XTAL1 and output XTAL2 connect the internal oscillator to the external crystal. The oscillator provides an inverter and a feedback element. An external TTL clock signal may be fed to the input XTAL1, leaving XTAL2 open. By using the RSTIN pin M2 can be put into the well defined reset condition either at power-up or upon external events like a hardware failure or manual reset. The internal reset signal can be driven on output pin RSTOUT/COR. The chipselect signals CSDRAM, CSROM, CS3 are for general control of external memories. During reset an internal pull-up ensures an inactive (high) level on these outputs. CS3 can be used for a ROM. Signals MEMCLK, CLKEN are used to provide a clock and an enable signal for an external SDRAM. During reset an internal pull-down ensures an inactive (low) level on these outputs. CVBS1A, CVBS1B and CVBS2 can carry two analog composite video signals and act as inputs for the two data slicers. The video signal on channel 1 can be either differential (CVBS1A and CVBS1B) or single-ended (CVBS1A, CVBS1B to ground). R, G, B are analog outputs from the display generator. CORBLA is a signal which indicates whether a pixel created by M2 should be displayed or mixed with external video source (blanking function). At the same time this signal Users Manual 6 - 16 2000-06-15 SDA 6000 System Control & Configuration carries information on contrast reduction of this pixel. Alternatively BLANK can be generated as a separate output signal. COR can be generated separately as well, in which case no RSTOUT is available. HSYNC and VSYNC are bidirectional pins which are used to synchronize M2 to an external video source or to deliver a stable horizontal and vertical sync timing to external components. 6.6 XBUS Configuration Although the XBUS is not visible at the chip boundary, some registers have to be set to guarantee correct operation. The user has to program the XBUS-registers in the following way: Register SYSCON XADRS1 XADRS2 XADRS3 - XADRS6 (not used) ADDRSEL1 - ADDRSEL4 (not used) XBCON1 XBCON2 XBCON3 - XBCON6 (not used) BUSCON0 BUSCON1 - BUSCON4 (not used) XPERCON Value E444H 0E03H 0E83H 0000H 0000H 05BFH 05BFH 0000H 15B7H 0000H 0003H 6.7 Watchdog Timer The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock (fCPU), either divided by 2 or divided by 128. This 16-bit timer is realized as two concatenated 8-bit timers (see Figure 6-3). The upper 8 bits of the watchdog timer can be preset to a user-programmable value via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset on each service access. The following figure shows the WDT block diagram: Users Manual 6 - 17 2000-06-15 SDA 6000 System Control & Configuration WDT Control WDTREL /2 MUX Clear WDT Low Byte WDT High Byte WDTR fWDT DISWDT / 128 WDTIN UEB11133 Figure 6-3 WDT Block Diagram The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT, which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload value for the high byte of the timer and selects the input clock prescaling factor. After any software reset, external hardware reset (see note), or watchdog timer reset, the watchdog timer is enabled and starts counting up from 0000H with the frequency fCPU/2. The input frequency may be switched to fCPU/128 by setting bit WDTIN. The watchdog timer can be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT (End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions disables the execution of DISWDT. When the watchdog timer is not disabled via instruction DISWDT it will continue counting up, even during Idle Mode. If it is not serviced by the SRVWDT instruction by the time the count reaches FFFFH the watchdog timer will overflow and cause an internal reset. In this case the Watchdog Timer Reset Indication Flag (WDTR) in register WDTCON will be set. To prevent the watchdog timer from overflowing, it must be serviced periodically by the user software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog time WDT register with the preset value in bit field WDTREL, which is the high byte of the WDTCON register. Servicing the watchdog timer will also reset the WDTR bit. After being serviced the watchdog timer continues counting up from the value ( Users Manual 6 - 18 2000-06-15 SDA 6000 System Control & Configuration SRVWDT does not match the format for protected instructions, the Protection Fault Trap will be entered, rather than the instruction being executed. The time period for an overflow of the watchdog timer is programmable in two ways: * The input frequency of the watchdog timer can be selected via bit WDTIN in register WDTCON to be either fCPU/2 or fCPU/128. * The reload value WDTREL for the high byte of WDT can be programmed in register WDTCON. The period PWDT between servicing the watchdog timer and the next overflow can therefore be determined by the following formula: PWDT = (2(1 + Table 6-1 marks the possible ranges for the watchdog time which can be achieved using a certain CPU clock. Some numbers are rounded to 3 significant digits. Table 6-1 Reload Value in WDTREL Watchdog Time Ranges Prescaler for fCPU 2 (WDTIN = `0') 33.33 MHz FFH 7FH 00H 25.6 s 3.3 ms 6.55 ms 3 MHz 32.0 s 4.13 ms 8.19 ms 128 (WDTIN = `1') 33.33 MHz 1.64 ms 211 ms 419 ms 3 MHz 2.05 ms 264 ms 524 ms Note: For safety reasons, the user is advised to rewrite WDTCON each time before the watchdog timer is serviced. Here is the description of the Watchdog timer SFRs. WDTCON 15 14 13 12 11 10 9 8 7 - Reset Value: 00XXH 6 - 5 - 4 LHW R 3 SHW R 2 SW R 1 WDT R 0 WDT IN WDTREL(7 .. 0) rw r r r r rw Users Manual 6 - 19 2000-06-15 SDA 6000 System Control & Configuration Bit WDTIN Function Watchdog Timer Input Frequency Selection 0: Input frequency is fCPU/2 1: Input frequency is fCPU/128 Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruction. Software Reset Indication Flag Short Hardware Reset Indication Flag Long Hardware Reset Indication Flag Watchdog Timer Reload Value (for the high byte of WDT) WDTR SWR SHWR LHWR WDTREL (7 ... 0) Note: The reset value depends on the reset source (see description below). The execution of EINIT clears the reset indication flags. Note: When the reset output is enabled pin RSTOUT will be pulled low for the duration of the internal reset sequence upon a watchdog timer reset. WDT Timer Register The WDT register contains the current count value of the Watchdog Timer. WDT 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 WDT(15 .. 0) r Note: This register in a read-only register. Write access can be performed to this register, during test mode only. Reset Source Indication The reset indication flags in register WDTCON provide information on the source of the last reset. As M2 starts executing from location 00'0000H after any possible reset event, the initialization software may check these flags in order to determine if the recent reset event was triggered by an external hardware signal (via RSTIN), by software itself or by an overflow of the watchdog timer. The initialization (and also the further operation) of the microcontroller system can thus be adapted to the respective circumstances, e.g. a special routine may verify the software integrity after a watchdog timer reset. Users Manual 6 - 20 2000-06-15 SDA 6000 System Control & Configuration The reset indication flags are not mutually exclusive, e.g. more than one flag may be set after reset depending on its source. The table below summarizes the possible combinations: Table 6-2 Reset Indication Flag Combinations Reset Indication Flags Reset Source Long Hardware Reset Short Hardware Reset Software Reset Watchdog Timer Reset LHWR X * * * SHWR X X * * SWR X X X X WDTR - - - X Note: *) When the reset output is enabled, the indicated flags are also set in the respective reset case. The WDTCON reset value will then be different from the table value. Note: The listed reset values for WDTCON assume the reserved bits as `0'. Long Hardware Reset is indicated when the RSTIN input is still sampled low (active) at the end of a hardware triggered internal reset sequence. Short Hardware Reset is indicated when the RSTIN input is sampled high (inactive) at the end of a hardware triggered internal reset sequence. Software Reset is indicated after a reset triggered by the execution of instruction SRST. Watchdog Timer Reset is indicated after a reset triggered by an overflow of the watchdog timer. Note: When reset output is enabled the RSTOUT pin is pulled low for the duration of the internal reset sequence upon any sort of reset. Therefore a long hardware reset (LHWR) will be recognized in any case. 6.8 Bootstrap Loader The bootstrap loader of M2 works in the same way as implemented in other C16x derivatives. It provides a mechanism to load the start-up program, which is executed after reset, via a serial interface (ASC). In this case no external (ROM) memory is required. The bootstrap loader moves code/data into the internal RAM, but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine. Users Manual 6 - 21 2000-06-15 SDA 6000 System Control & Configuration RSTIN P4.0 1) 2) RxD0 3) TxD0 4) CSP:IP Int. Boot ROM BSL-routine BSL initialization time, > 1.5 s @ fCPU = 33 MHz Zero byte (1 start bit, eight '0' data bits, 1 stop bit), sent by host 3) Identification byte (D5H ) sent by M2 4) 32 bytes of code/data, sent by host 1) 2) UET11134 32 bytes User Software Figure 6-4 Bootstrap Loader Sequence The M2 enters BSL mode, if pin P4.0 is sampled low at the end of a hardware reset. When M2 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Register SYSCON: Context Pointer CP: Register STKUN: Stack Pointer SP: Register STKOV: Register S0CON: Register BUSCON0: Register S0BG: P3.10/TXD0: DP3.10: Disabled 0C00H FA00H FA40H FA40H FA0CH 0 <-> C 8001H according to start-up config. according to `00' byte `1' `1' Other than after a normal reset the watchdog timer is disabled, therefore the bootstrap loading sequence is not time limited. Pin TXD0 is configured as output. The configuration (e.g. the accessibility) of the M2's memory areas after reset in Bootstrap-Loader mode differs from the standard case. Accesses to the external ROM area are partly redirected, Users Manual 6 - 22 2000-06-15 SDA 6000 System Control & Configuration while the M2 is in BSL mode. All code fetches to segment 0 are made from the special Boot-ROM, while data accesses read from the external user ROM. 6.9 Identification Registers A set of 8 identification registers are provided to offer information on the chip as manufacturer, chip type and its memory (EEPROM, OTP, DRAM or Flash memory) properties, and information on the CSCU (type of module, redesign state). The ID registers are read only registers. These registers are: * * * * * IDMANUF, for manufacturer and department identification, IDCHIP, for device identification and revision code, IDMEM, for identification of on-chip program memory (type, size), IDMEM2, for identification of additional EEPROM, OTP, DRAM or Flash memory, IDPROG, for identification of programming/erasing voltage of on-chip program memory, * IDRT, redesign tracking register for identification of revisions and laser cuts. Besides, some other registers provide identification of some parts of the M2. These registers are hardwired inside the M2. * CPUID, for CPU identification, * IDSCU, for CSCU identification, * DIPX version bit field, for OCDS identification. 6.9.1 IDMANUF 15 14 System Identification Reset Value: XXXXH 13 12 11 10 MANUF These identific ID register description 9 8 7 6 5 4 3 2 DEPT 1 0 r r Users Manual 6 - 23 2000-06-15 SDA 6000 System Control & Configuration Bit MANUF Function Manufacturer This is the JEDEC normalized manufacturer code. 0C1H: Infineon Technologies 020H: SGS-Thomson Department Indicates the department within Infineon Technologies. 00H: HL MC 01H: HL CAD Macrocells 02H: HL IT Reset Value: XXXXH 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DEPT IDCHIP 15 14 CHIPID Chip Revision Number r r Bit Revision CHIPID Function Device Revision Code Identifies the device step where the first release is marked `01H'. Device Identification Identifies the device name. Please refer to the association table. Reset Value: XXXXH 13 Type IDMEM 15 14 12 11 10 9 8 7 6 Size 5 4 3 2 1 0 r r IDMEM2 15 14 13 Type Reset Value: XXXXH 12 11 10 9 8 7 6 Size 5 4 3 2 1 0 r r Note: IDMEM2 describes the second block of (program) memory. E.g. a device may contain Flash and EEPROM or DRAM sections. Static RAM modules are not described with ID registers. Users Manual 6 - 24 2000-06-15 SDA 6000 System Control & Configuration Bit Size Function Size of On-chip Program Memory The size of the implemented program memory in terms of 4 K blocks, i.e. Memory-size = 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PROGVPP PROGVDD Type IDPROG 15 14 r r Bit PROGVDD Function Programming VDD Voltage1) The voltage of the standard power supply pins required when programming or erasing (if applicable) the on-chip program memory. Formula: VDD = 20 x PROGVPP Note: IDRT 15 LC 1) Devices that incorporate memories which cannot be programmed outside the factory will indicate `00H' in both bit fields. Reset Value: XXXXH 14 RA 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 RIX 0 r r - - - - - - - - - - - r Note: The Redesign Tracing register IDRT is not commonly specified. It is protected against standard read accesses via the function testmode (Testmode A). Users Manual 6 - 25 2000-06-15 SDA 6000 System Control & Configuration Bit RIX Function Redesign Index 0: This device is the original "Revision". else: This device has experienced minor changes that are not reflected to the customer by the "Revision" bit field. Redundancy Activation 0: This device is as it was manufactured. 1: Redundant memory structures have been activated. Laser Correction 0: This device is as it was manufactured. 1: This device has been laser corrected. RA LC 6.9.2 CPU Identification The CPU is identified by the CPUID register. This register is only implemented on STARLIB versions of the M2 Rev. 2.0. CPUID 15 14 13 12 11 10 9 8 7 6 CBC Rev. Reset Value: 0061H 5 4 3 2 Core ID 1 0 - - - - r Bit CBC Rev. Core ID Function CBC Revision number currently 011B Core Identification number for the C166 CBC the value is 00001B The SCU provides a specific read-only identification register for its own module type and revision identification. IDSCU 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SCU Module Number SCU Revision Number r r For Rev. 2.0 derivatives, the current value is 0000H. Users Manual 6 - 26 2000-06-15 SDA 6000 System Control & Configuration 6.10 Parallel Ports M2 provides up to 30 input/outputs, 6 output and 6 input multiple purpose ports. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of two I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. Most of the port lines have programmable alternate input or output functions associated with them (GPT1/GPT2, external interrupts, I2C-bus, analog inputs for A/D converter, SSC-interface or ASC-interface). All port lines that are not used for these alternate functions may be used as general purpose I/O lines. Ports of M2 are 3.3 V tolerant and can deliver a 3.3 V output voltage (refer also to Chapter 14). Data Input/ Output Registers Direction Control Registers Open Drain Control Registers Special Control Registers P2 P3 P4 P5 P6 DP2 DP3 ODP3 P5BEN DP6 ODP6 ALTSELOP6 UEA11135 Figure 6-5 Port 0 Portlogic Register Overview Port 0 does not exist due to the dedicated memory bus structure of M2. Port 1 Port 1 does not exist due to the dedicated memory bus structure of M2. Port 2 Port 2 is an 8-bit bidirectional I/O port which can also serve as fast external interrupt input (sample rate is 30 ns). Users Manual 6 - 27 2000-06-15 SDA 6000 System Control & Configuration P2 15 14 13 12 11 10 9 P2.9 Reset Value: 0000H 8 P2.8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 rw rw rw rw rw rw rw rw Bit P2.y DP2 15 DP2. 15 Function Port data register P2 bit y. Reset Value: 0000H 14 DP2. 14 13 DP2. 13 12 DP2. 12 11 DP2. 11 10 DP2. 10 9 DP2. 9 8 DP2. 8 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - rw rw rw rw rw rw rw rw Bit DP2.y Function Port direction register DP2 bit y DP2.y = 0: Port line P2.y is an input (high-impedance). DP2.y = 1: Port line P2.y is an output. Users Manual 6 - 28 2000-06-15 SDA 6000 System Control & Configuration Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3. All port lines can be switched into push/pull or open drain mode via the open drain control register ODP3. Due to pin limitations register bit P3.14 is not connected to any pin. P3 15 P3.15 Reset Value: 0000H 14 - 13 12 11 10 9 P3.9 8 P3.8 7 P3.7 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0 P3.13 P3.12 P3.11 P3.10 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit P3.y Function Port data register P3 bit y. Note: Register bit P3.14 is not connected to an I/O pin. DP3 15 DP3. 15 Reset Value: 0000H 14 - 13 DP3. 13 12 DP3. 12 11 DP3. 11 10 DP3. 10 9 DP3. 9 8 DP3. 8 7 DP3. 7 6 DP3. 6 5 DP3. 5 4 DP3. 4 3 DP3. 3 2 DP3. 2 1 DP3. 1 0 DP3. 0 rw - rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit DP3.y Function Port direction register DP3 bit y DP3.y = 0: Port line P3.y is an input (high-impedance). DP3.y = 1: Port line P3.y is an output. Reset Value: 0000H 14 - ODP3 15 ODP3. 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. ODP3. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw - rw rw rw rw rw rw rw rw rw rw rw rw rw rw Users Manual 6 - 29 2000-06-15 SDA 6000 System Control & Configuration Bit ODP3.y Function Port 3 Open Drain control register bit y ODP3.y = 0: Port line P3.y output driver in push/pull mode. ODP3.y = 1: Port line P3.y output driver in open drain mode. Alternate Functions of Port 3 The pins of Port 3 serve various functions which include external timer control lines and the 3 serial interfaces. The table below summarizes the alternate functions of Port 3. Port 3 Pin Alternate Function P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.15 Port 4 Port 4 is a 6-bit output port. Because of its high frequency requirements in the alternate function mode, it has different electrical characteristics than the other ports. During reset, the user specific portion of the system start-up configuration is input via Port 4. The complete configuration (user specific as well as hardwired settings) can be read at runtime from register RP0H. For a detailed description refer to Chapter 6.1. SCL0 SDA0 CAPIN T3OUT T3EUD T4IN T3IN T2IN MRST MTSR TxD0 RxD0 --SCLK --LED2 I2C - bus clock line 0 I2C - bus data line 0 GPT2 capture input Timer 3 Toggle output Timer 3 External Up/Down input Timer 4 Count input Timer 3 Count input Timer 2 Count input SSC Master receive/Slave transmit SSC Master transmit/Slave receive ASC0 Transmit data output ASC0 Receive data input No alternate function SSC Shift Clock input/output Not implemented. No pin assigned! No alternate function Users Manual 6 - 30 2000-06-15 SDA 6000 System Control & Configuration P4L (during reset) 15 - Reset Value: XXXXH 11 - 14 - 13 - 12 - 10 - 9 - 8 - 7 - 6 - 5 P4L.5 4 3 2 1 0 P4L.4 P4L.3 P4L.2 P4L.1 P4L.0 r r r r r r Bit P4L.0 Function BSLENA (Boot Strap Load Enable) P4L.0 = 1: Boot strap loader enabled P4L.0 = 0: Boot strap loader disabled CSENA (Chip Select Enable) P4L.1 = 1: P4.5 configured as general purpose pin P4L.1 = 0: P4.5 configured as CS3 Reserved SALSEL(2 ... 0) (Select Number of Address Lines) see explanation below Reset Value: 0000H 14 - P4L.1 P4L.2 P4L.(5 ... 3) P4 15 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 P4.5 4 P4.4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 rw rw rw rw rw rw Bit P4.y Function Port data register P4 bit.y Alternate Functions of Port 4 During external bus cycles that use segmentation (e.g. an address space above 128 KByte), a number of Port 4 pins may output the segment address lines and activate the third chip select signal (A(20 ... 16) and CS3). The number of pins that is used for segment address output determines the external address space which is directly accessible. The other pins of Port 4 (if any) may be used for general purpose output. If segment address lines are selected, the alternate function of Port 4 may be necessary to access e.g. external memory directly after reset. For this reason Port 4 will be automatically switched to this alternate function. Users Manual 6 - 31 2000-06-15 SDA 6000 System Control & Configuration The number of segment address lines is selected via P4 during reset. The selected value can be read from bit field SALSEL and CSENA of register RP0H e.g. in order to check the configuration during run time. Port 4 Altern. Altern. Altern. Altern. Altern. SALSEL = 010 or Pin Function Function Function Function Function 001 or 000 SALSEL = 111 SALSEL = 110 SALSEL = 101 SALSEL = 100 SALSEL = 011 P4.0 P4.1 P4.2 P4.3 P4.4 A16 A17 A18 A19 A20 A16 A17 A18 A19 Gen. Purp. I/O A16 A17 A18 Gen. Purp. I/O Gen. Purp. I/O A16 A17 Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O A16 Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Gen. Purp. I/O Port 4 Pin P4.5 Port 5 Altern. Function CSENA = 0 CS3 Altern. Function CSENA = 1 Gen. Purp. I/O Port 5 is a 6-bit input port. P5 15 14 13 - Reset Value: 0000H 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 P5.3 2 P5.2 1 P5.1 0 P5.0 P5.15 P5.14 r r r r r r Bit P5.y Function Port data register P5 bit y (read only). Alternate Functions of Port 5 Port 5.3 ... P5.0 is also connected to the input multiplexer of the A/D Converter. These lines can accept analog signals (AN3 ... AN0) that can be converted by the ADC. Port 5.15 and 5.14 also serve as external timer control lines for GPT1 and GPT2. Users Manual 6 - 32 2000-06-15 SDA 6000 System Control & Configuration Port 5 Pin Alternate Function P5.0 P5.1 P5.2 P5.3 P5.14 P5.15 P5BEN 15 - ANA0 ANA1 ANA2 ANA3 T4EUD T2EUD Analog Input 0 (Wake Up Function) Analog Input 1 Analog Input 2 Analog Input 3 Timer 4 External Up/Down Input Timer 2 External Up/Down Input Reset Value: 0000H 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 P5B EN.3 2 P5B EN.2 1 P5B EN.1 0 P5B EN.0 rw rw rw rw Bit P5BEN.y Function Input Functionality Control Bit P5BEN.y = 0: Analog Input Functionality. P5BEN.y = 1: Digital Input Functionality. Port 6 If this 7-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP6. The port lines can be switched into push/pull or open drain mode via the open drain control register ODP6. P6 15 - Reset Value: 0000H 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 P6.6 5 P6.5 4 P6.4 3 P6.3 2 P6.2 1 P6.1 0 P6.0 rw rw rw rw rw rw rw Bit P6.y Function Port data register P6 bit y. Users Manual 6 - 33 2000-06-15 SDA 6000 System Control & Configuration DP6 15 - Reset Value: 0000H 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 2 1 0 DP6.6 DP6.5 DP6.4 DP6.3 DP6.2 DP6.1 DP6.0 rw rw rw rw rw rw rw Bit DP6.y Function Port direction register DP6 bit y. DP6.y = 0: Port line P6.y is an input (high-impedance). DP6.y = 1: Port line P6.y is an output. Reset Value: 0000H 14 - ODP6 15 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 2 1 0 ODP6. ODP6. ODP6. ODP6. ODP6. ODP6. ODP6. 6 5 4 3 2 1 0 rw rw rw rw rw rw rw Bit ODP6.y Function Port 6 Open Drain control register bit y ODP6.y = 0: Port line P6.y output driver in push/pull mode ODP6.y = 1: Port line P6.y output driver in open drain mode Alternate Functions of Port 6 The table below summarizes the alternate functions of Port 6. Port 6 Pin Alternate Function P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 TRIG_IN TRIG_OUT SCL1 SDA1 SDA2 Trigger Input for Emulation Trigger output for Emulation no alternate function I2C Bus Clock Line 1 I2C Bus Data Line 1 no alternate function I2C Bus Data Line 2 Users Manual 6 - 34 2000-06-15 SDA 6000 System Control & Configuration ALTSEL0P6 15 - Reset Value: 0000H 12 - 14 - 13 - 11 - 10 - 9 - 8 - 7 - 6 SEL P6.6 5 SEL P6.5 4 SEL P6.4 3 SEL P6.3 2 SEL P6.2 1 SEL P6.1 0 SEL P6.0 rw rw rw rw rw rw rw Bit SELP6.y Function Alternate Function Control Bit SELP6.y = 0: General Purpose Port Functionality enabled for Line P6.y. SELP6.y = 1: Alternate Function enabled for Line P6.y. Users Manual 6 - 35 2000-06-15 Peripherals SDA 6000 Peripherals 7 Peripherals All of the peripherals described in the following paragraphs are clocked with the same clock as the CPU (fhw_clk). Depending on the mode (normal or Idle), this frequency is 33.33 MHz or 3 MHz. 7.1 General Purpose Timer Unit The General Purpose Timer Unit (GPT) represents very flexible multifunctional timer structures which may be used for timing, event counting, pulse width measurement, pulse generation, frequency multiplication, and other purposes. They incorporate five 16-bit timers that are grouped into the two timer blocks GPT1 and GPT2. Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode, or may be concatenated with another timer of the same block. Block 1 contains 3 timers/counters with a maximum resolution of fhw_clk/4. The auxiliary timers of GPT1 may be optionally configured as reload or capture registers for the core timer. Block 2 contains 2 timers/counters with a maximum resolution of fhw_clk/2. An additional CAPREL register supports capture and reload operations with extended functionality, and its core timer T6 may be concatenated with the timers from the CAPCOM unit (T0 and T1). The following enumeration summarizes all features to be supported: Timer Block 1: * * * * * fhw_clk/4 maximum resolution 3 independent timers/counters Timers/counters can be concatenated 4 operating modes (timer, gated timer, counter, incremental) Separate interrupt nodes Timer Block 2: * * * * * * fhw_clk/2 maximum resolution 2 independent timers/counters Timers/counters can be concatenated 3 operating modes (timer, gated timer, counter) Extended capture/reload functions via 16-bit Capture/Reload register CAPREL Separate interrupt nodes 7.1.1 Functional Description of Timer Block 1 All three timers of block 1 (T2, T3, T4) can run in 4 basic modes, which are timer, gated timer, counter and incremental interface mode. All timers can either count up or down. Users Manual 7-3 2000-06-15 SDA 6000 Peripherals Each timer has an input line (TxIN) associated with it which serves as the gate control in gated timer mode, or as the count input in counter mode. The count direction (Up / Down) may be programmed via software or dynamically altered by a signal at an external control input line (TxEUD). An overflow/underflow of core timer T3 is indicated by the output toggle latch T3OTL whose state may be output on related line T3OUT. The auxiliary timers T2 and T4 may additionally be concatenated with the core timer, or used as capture or reload registers for the core timer. Concatenation of T3 with other timers is provided through line T3OTL. The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2, T3, or T4, which are located in the non-bitaddressable SFR space. When any of the timer registers are written to by the CPU in the state immediately before a timer increment, decrement, reload, or capture is to be performed, the CPU write operation has priority in order to guarantee correct results. T2EUD U/D 2n : 1 T2 Mode Control Reload Capture T3OTL GPT1 Timer T2 Interrupt Request f hw_clk T2IN f hw_clk 2n : 1 T3 Mode Control Interrupt Request T3IN GPT1 Timer T3 U/D T3EUD T3OTL Capture Reload T4IN f hw_clk T4EUD 2n : 1 T4 Mode Control GPT1 Timer T4 U/D Interrupt Request UEB11195 Figure 7-1 Structure of Timer Block 1 Core Timer T3 The operation of the core timer T3 is controlled by its bit-addressable control register T3CON. Users Manual 7-4 2000-06-15 SDA 6000 Peripherals Run Control The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit). Setting bit T3R will start the timer, clearing T3R stops the timer. In gated timer mode, the timer will only run if T3R is set and the gate is active (high or low, as programmed). Note: When bit T2RC/T4RC in timer control register T2CON/T4CON is set, T3R will also control (start and stop) auxiliary timer T2/T4. Count Direction Control The count direction of the core timer can either be controlled by software or by the external input line T3EUD (Timer T3 External Up/Down Control Input). These options are selected by bits T3UD and T3UDE in control register T3CON. When the up/down control is executed by software (bit T3UDE = `0'), the count direction can be altered by setting or clearing bit T3UD. When T3UDE = `1', line T3EUD is selected to be the controlling source of the count direction. However, bit T3UD can still be used to reverse the actual count direction, as shown in the table below. If T3UD = `0' and line T3EUD shows a low level, the timer is counting up. With a high level T3EUD, the timer is counting down. If T3UD = `1', a high level at line T3EUD specifies counting up, and a low level specifies counting down. The count direction can be changed regardless of whether the timer is running or not. When line T3EUD is used as external count direction control input, its associated port pin must be configured as input. Table 7-1 X X 0 1 0 1 Core Timer T3 Count Direction Control Bit T3UD 0 1 0 0 1 1 Count Direction Count Up Count Down Count Up Count Down Count Down Count Up 0 0 1 1 1 1 Line T3EUD Bit T3UDE Note: The direction control works in the same way for core timer T3 and for auxiliary timers T2 and T4. Therefore the lines and bits are named Tx ... Timer 3 Overflow/Underflow Monitoring An overflow or underflow of timer T3 will clock the overflow toggle latch T3OTL in control register T3CON. T3OTL can also be set or reset by software. Bit T3OE (Overflow/ Users Manual 7-5 2000-06-15 SDA 6000 Peripherals Underflow Output Enable) in register T3CON enables the state of T3OTL to be monitored via an external line T3OUT. If this line is linked to an external port pin, which has to be configured as output, T3OTL can be used to control external HW. In addition, T3OTL can be used in conjunction with the timer over/underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4. For this purpose, the state of T3OTL does not have to be available at any port pin, because an internal connection is provided for this option. Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `000B'. In this mode, T3 is clocked with the system clock fhw_clk divided by a programmable prescaler, which is controlled by bit field T3I and BPS1. The input frequency fT3 for timer T3 and its resolution rT3 are scaled linearly with lower module clock frequencies, as can be seen from the following formula: fT3 = fhw_clk BPS1 x 2 BPS1 x 2 Table 7-2 gives an overview for timer resolutions depending on prescaler factors. Table 7-2 fMOD = 33.33 MHz Timer Input Selection T2I / T3I / T4I 000B 000B 001B 010B 0 32 1.04 MHz 960 ns 011B 0 64 100B 0 128 101B 0 256 110B 0 512 111B 0 1024 32.55 kHz 30.72 s 2.01 s FM = Prescaler factor 1 4 0 8 0 16 2.08 MHz 480 ns Input Frequency 2.08 4.16 MHz MHz Resolution Period 120 ns 7.86 ms 240 ns 521.83 260.41 130.20 65.10 kHz kHz kHz kHz 1.92 s 3.84 s 7.68 s 503 ms 15.36 s 1 s 15.72 31.45 62.91 125.82 251.6 ms ms ms ms ms This formula also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode. Users Manual 7-6 2000-06-15 SDA 6000 Peripherals BPS1 TxI f hw_clk 2n : 1 TxR TxUD 0 MUX Core Timer Tx Up/ Down Interrupt Request TxEUD EXOR 1 TxUDE x=3 UEB11196 Figure 7-2 Block Diagram of Core Timer T3 in Timer Mode Timer 3 in Gated Timer Mode The gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `010B' or `011B'. Bit T3M.0 (T3CON.3) selects the active level of the gate input. In gated timer mode the same options are available for the input frequency as for the timer mode. However, the input clock to the timer in this mode is gated by the external input line T3IN (Timer T3 External Input); an associated port pin should be configured as input. BPS1 TxI f hw_clk 2n : 1 TxIN MUX TxM TxUD 0 MUX TxR Core Timer Tx Up/ Down TxOTL TxOE TxOUT Interrupt Request x=3 UEB11197 TxEUD XOR 1 TxUDE Figure 7-3 Users Manual Block Diagram of Core Timer T3 in Gated Timer Mode 7-7 2000-06-15 SDA 6000 Peripherals If T3M = `010B', the timer is enabled when T3IN shows a low level. A high level at this line stops the timer. If T3M = `011B', line T3IN must have a high level in order to enable the timer. In addition, the timer can be turned on or off by software using bit T3R. The timer will only run, if T3R is set and the gate is active. It will stop, if either T3R is cleared or the gate is inactive. Note: A transition of the gate signal at line T3IN does not cause an interrupt request. Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `001B'. In counter mode, timer T3 is clocked by a transition at the external input line T3IN. The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and negative transition at this line. Bit field T3I in control register T3CON selects the triggering transition (see table below). Edge Select TxOFL Core Timer Tx TxR Up/ Down TxOTL TxOE TxOUT TxIN TxI TxUD 0 MUX TxEUD XOR 1 TxUDE UEB11198 Interrupt Request x=3 Figure 7-4 Table 7-3 T3I 000 001 010 011 1XX Users Manual Block Diagram of Core Timer T3 in Counter Mode Core Timer T3 (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 is disabled Positive transition (rising edge) on T3IN Negative transition (falling edge) on T3IN Any transition (rising or falling edge) on T3IN Reserved. Do not use this combination 7-8 2000-06-15 SDA 6000 Peripherals For counter operation, a port pin associated to line T3IN must be configured as input. The maximum input frequency which is allowed in counter mode is fhw_clk/8 (BPS1 = `01'). To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized, its level should be held high or low for at least 4 fhw_clk cycles (BPS1 = `01') before it changes. Timer 3 in Incremental Interface Mode Incremental Interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to `110B' or `111B'. In Incremental Interface mode the two inputs associated with timer T3 (T3IN, T3EUD) are used to interface to an incremental encoder. T3 is clocked by each transition on one or both of the external input lines which gives 2-fold or 4-fold the resolution of the encoder input. T3IN Edge Select T3I T3R T3 Edge Timer T3 Up/ Down T3 RDIR T3OTL T3OUT T3OE Interrupt Request Edge Interrupt T3M Change Detection T3UD 0 MUX 1 T3UDE T3 CHDIR T3M Rotation Interrupt T3EUD Phase Detect XOR UEB11199 Figure 7-5 Block Diagram of Core Timer T3 in Incremental Interface Mode The T3I bit field in control register T3CON selects the triggering transitions (see Table 7-4). In this mode, the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal. Depending on the chosen Incremental Interface Mode, rotation detection `110B' or edge detection `111B', an interrupt is generated. For the rotation detection, an interrupt will be generated each time the count direction of timer T3 changes. For the edge detection an interrupt will be Users Manual 7-9 2000-06-15 SDA 6000 Peripherals generated each time a count action for timer T3 occurs. Count direction, changes in the count direction and count requests are monitored through the status bits T3RDIR, T3CHDIR and T3EDGE in register T3CON. T3 is modified automatically according to the speed and the direction of the incremental encoder. Therefore, the contents of the T3 timer always represents the encoder's current position. Table 7-4 T3I 000 001 010 011 1XX Core Timer T3 (Incremental Interface Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter T3 stops. Any transition (rising or falling edge) on T3IN. Any transition (rising or falling edge) on T3EUD. Any transition (rising or falling edge) on any T3 input (T3IN or T3EUD). Reserved. Do not use this combination. The incremental encoder can be connected directly to the microcontroller without external interface logic. In a standard system, however, comparators will be employed to convert the encoder's differential outputs (e.g. A, A) to digital signals (e.g. A). This greatly increases noise immunity. Note: The third encoder output T0, which indicates the mechanical zero position, may be connected to an external interrupt input and trigger a reset of timer T3. A A + - A T3 Input External Encoder B B + - B T3 Input Microcontroller T0 T0 + - T0 Interrupt Signal Conditioning UED11136 Figure 7-6 Interfacing the Encoder to the Microcontroller For incremental interface operation the following conditions must be met: * The T3M bit field must be `110B' or `111B'. * Pins associated with lines T3IN and T3EUD must be configured as input. * The T3UDE bit must be set to enable automatic direction control. Users Manual 7 - 10 2000-06-15 SDA 6000 Peripherals The maximum input frequency which is allowed in incremental interface mode is fhw_clk/ 8 (BPS = 01). To ensure that a transition of any input signal is correctly recognized, its level should be held high or low for at least 4 fhw_clk cycles (BPS = 01) before it changes. In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change, which corresponds to the rotation direction of the connected sensor. Table 7-5 summarizes the possible combinations. Table 7-5 Core Timer T3 (Incremental Interface Mode) Count Direction T3IN Input Rising Down Up Falling Up Down Rising Up Down T3EUD Input Falling Down Up Level on Respective other Input High Low The figures below give examples of T3's operation, visualizing count signal generation and direction control. It also shows how input jitter is compensated, which might occur if the sensor rests near to one of its switching points. Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behavior assuming that T3 counts upon any transition on any input, i.e. T3I = '011B'. UET11137 Figure 7-7 Evaluation of the Incremental Encoder Signals Users Manual 7 - 11 2000-06-15 SDA 6000 Peripherals Forward T3IN T3EUD Jitter Backward Jitter Forward Contents of T3 Up Down Up Note: This example shows the timer behavior assuming that T3 counts upon any transition on input T3IN, i.e. T3I = '001B'. UET11138 Figure 7-8 Evaluation of the Incremental Encoder Signals Note: Timer T3, operating in incremental interface mode, automatically provides information on the sensor's current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods. Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality. They can be configured for timer, gated timer, counter, or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3. In addition to these 4 counting modes, the auxiliary timers can be concatenated with the core timer, or they may be used as reload or capture registers in conjunction with the core timer. The individual configuration for the T2 and T4 timers is determined by their bit-addressable control registers T2CON and T4CON, which are both organized identically. Note that functions which are present in all 3 timers of timer block 1 are controlled in the same bit positions and in the same manner in each of the specific control registers. Run control for auxiliary timers T2 and T4 can be handled by the associated Run Control Bit T2R, T4R in register T2CON/T4CON. Alternatively, a remote control option (T2RC, T4RC set) may be enabled to start and stop T2/T4 via the run bit T3R of core timer T3. Users Manual 7 - 12 2000-06-15 SDA 6000 Peripherals Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode, their operation is the same as described for the core timer T3. The descriptions, figures and tables apply accordingly with two exceptions: * There is no TxOUT output line for T2 and T4. * Overflow/Underflow Monitoring is not supported (no output toggle latch). Timers T2 and T4 in Counter Mode In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input line TxIN, or by a transition of timer T3's output toggle latch T3OTL. Edge Select TxIN TxR TxI TxUD 0 MUX TxEUD XOR 1 TxUDE Auxiliary Timer Tx Up/ Down Interrupt Request x = 2, 4 UEB11200 Figure 7-9 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and negative transition at either the respective input line, or at the output toggle latch T3OTL. Bit field TxI in the respective control register TxCON selects the triggering transition (see Table 7-6). Users Manual 7 - 13 2000-06-15 SDA 6000 Peripherals Table 7-6 T2I/T4I X00 001 010 011 101 110 111 Auxiliary Timer (Counter Mode) Input Edge Selection Triggering Edge for Counter Increment/Decrement None. Counter Tx is disabled Positive transition (rising edge) on TxIN Negative transition (falling edge) on TxIN Any transition (rising or falling edge) on TxIN Positive transition (rising edge) of output toggle latch T3OTL Negative transition (falling edge) of output toggle latch T3OTL Any transition (rising or falling edge) of output toggle latch T3OTL Note: Only state transitions of T3OTL which are caused by the overflows/underflows of T3 will trigger the counter function of T2/T4. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. For counter operation, an external pin associated to line TxIN must be configured as input. The maximum input frequency which is allowed in counter mode is fhw_clk/8 (BPS1 = `01'). To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized, its level should be held for at least 4 fhw_clk cycles (BPS1 = `01') before it changes. 7.1.1.1 Timer Concatenation Using the output toggle latch T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer. Depending on which transition of T3OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer/counter. * 32-bit Timer/Counter: If both positive and negative transitions of T3OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T3. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T3. This configuration forms a 33-bit timer (16-bit core timer + T3OTL + 16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. In this case T3 can operate in timer, gated timer or counter mode. Users Manual 7 - 14 2000-06-15 SDA 6000 Peripherals BPS1 TyI f hw_clk 2n : 1 TyR Core Timer Ty Up/Down TyOTL TyOE TyOUT *) Edge Select Interrupt Request Auxiliary Timer Tx TxR TxI TxIR Interrupt Request x = 2, 4 y = 3 UES11201 Note: Line `*' is only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 7-10 Concatenation of Core Timer T3 and an Auxiliary Timer Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to `100B'. In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register, triggered by one of two different signals. The trigger signal is selected the same way as the clock source for counter mode (see Table 7-6), i.e. a transition of the auxiliary timer's input or the output toggle latch T3OTL may trigger the reload. Note: When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Users Manual 7 - 15 2000-06-15 SDA 6000 Peripherals Source/Edge Select x = 2, 4 Reload Register Tx Interrupt Request TxIN TxI *) Input Clock Core Timer T3 Interrupt Request Up/Down T3OTL T3OUT T3OE UES11202 Note: Line `*' is only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 7-11 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal, T3 is loaded with the contents of the respective timer register (T2 or T4) and the interrupt request flag (T2IR or T4IR) is set. Note: When a T3OTL transition is selected for the trigger signal, also the interrupt request flag T3IR will be set upon a trigger, indicating T3's overflow or underflow. Modifications of T3OTL via software will NOT trigger the counter function of T2/T4. The reload mode triggered by T3OTL can be used in a number of different configurations. Depending on the selected active transition the following functions can be performed: * If both a positive and a negative transition of T3OTL are selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows. This is the standard reload mode (reload on overflow/ underflow). * If either a positive or a negative transition of T3OTL is selected to trigger a reload, the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow. * Using this "single-transition" mode for both auxiliary timers allows very flexible pulse width modulation (PWM) to be performed. One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL, the other is programmed for a reload on a negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. Users Manual 7 - 16 2000-06-15 SDA 6000 Peripherals Figure 7-12 shows an example of the generation of a PWM signal using the alternate reload mechanism. T2 defines the high time of the PWM signal (reloaded on positive transitions) and T4 defines the low time of the PWM signal (reloaded on negative transitions). The PWM signal can be output on line T3OUT if the control bit T3OE is set. With this method the high and low time of the PWM signal can be varied in a wide range. Note: The output toggle latch T3OTL is accessible via software and may be changed, if required, to modify the PWM signal. However, this will NOT trigger the reloading of T3. Note: An associated port pin linked to line T3OUT should be configured as output. Reload Register T2 Interrupt Request *) Input Clock T2I T3OUT Core Timer T3 T3OTL Up/Down *) T3OE Interrupt Request Interrupt Request Reload Register T4 T4I UES11203 Note: Lines `*' are only affected by over/underflows of T3, but NOT by software modifications of T3OTL. Figure 7-12 GPT1 Timer Reload Configuration for PWM Generation Note: Although it is possible, selecting the same reload trigger event for both auxiliary timers should be avoided. In this case both reload registers would try to load the core timer at the same time. If this combination is selected, T2 is disregarded and the contents of T4 reloaded. Users Manual 7 - 17 2000-06-15 SDA 6000 Peripherals Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to `101B'. In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input line TxIN. The capture trigger signal can be a positive, a negative, or both a positive and a negative transition. The two least significant bits of bit field TxI are used to select the active transition (see table in the counter mode section), while the most significant bit, TxI.2, is irrelevant for capture mode. It is recommended to keep this bit cleared (TxI.2 = `0'). Note: When programmed for capture mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Edge Select x = 2, 4 Capture Register Tx Interrupt Request TxIN TxI Input Clock Core Timer T3 Interrupt Request Up/Down T3OTL T3OUT T3OE UES11204 Figure 7-13 Auxiliary Timer of Timer Block 1 in Capture Mode Upon a trigger (selected transition) at the corresponding input line TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set. Note: The direction control for T2IN and for T4IN must be set to `Input', and the level of the capture trigger signal should be kept high or low for at least 4 fhw_clk (BPS1 = `01') cycles before it changes, to ensure correct edge detection. Users Manual 7 - 18 2000-06-15 SDA 6000 Peripherals 7.1.2 Functional Description of Timer Block 2 Timer block 2 includes the two timers T5 (referred to as the auxiliary timer) and T6 (referred to as the core timer), and the 16-bit capture/reload register CAPREL. The count direction (Up / Down) may be programmed by software. The auxiliary timer T6 may be reloaded with the contents of CAPREL. The toggle bit (T6OTL) also supports the concatenation of T6 with auxiliary timer T5, while concatenation of T6 with other timers is provided through line T6OFL. Triggered by an external signal, the contents of T5 can be captured in register CAPREL, and T5 may optionally be cleared. Both timer T6 and T5 can count up or down, and the current timer value can be read or modified by the CPU in the non-bitaddressable SFRs T5 and T6. f hw_clk 2n : 1 T5 Mode Control U/D GPT2 Timer T5 Clear Capture Interrupt Request GPT2 CAPREL Interrupt Request CAPIN T3IN/ T3EUD MUX CT3 Clear GPT2 Timer T6 T6 Mode Control U/D T6OTL Interrupt Request f hw_clk 2n : 1 UES11205 Figure 7-14 Structure of Timer Block 2 Users Manual 7 - 19 2000-06-15 SDA 6000 Peripherals 7.1.2.1 Core Timer T6 The operation of the core timer T6 is controlled by its bit-addressable control register T6CON. Timer 6 Run Bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). Setting bit T6R will start the timer, clearing T6R stops the timer. Note: When bit T5RC is set, bit T6R will also control (start and stop) auxiliary timer T5. Count Direction Control The count direction of the core timer can be controlled by software. The count direction can be changed regardless of whether the timer is running or not. Table 7-7 Bit TxUD 0 1 Core Timer T6 Count Direction Control Count Direction Count Up Count Down Note: The direction control works the same for core timer T6 and for auxiliary timer T5. Therefore the lines and bits are named Tx ... Timer 6 Overflow/Underflow Monitoring An overflow or underflow of timer T6 will clock the toggle latch T6OTL in control register T6CON. T6OTL can also be set or reset by software. T6OTL can be used in conjunction with the timer over/underflows as an input for the counter function of the auxiliary timer T5. Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to `000B'. In this mode, T6 is clocked with the module clock divided by a programmable prescaler, which is selected by bit field T6I. The input frequency fT6 for timer T6 and its resolution rT6 are scaled linearly with lower clock frequencies fhw_clk, as can be seen from the following formula: fT6 = fhw_clk BPS2 x 2 rT6 [ms] = BPS2 x 2 Users Manual 7 - 20 2000-06-15 SDA 6000 Peripherals BPS2 T6I T6OFL f hw_clk 2n : 1 Core Timer T6 Up/ Down T6UD Interrupt Request T6OTL x=6 UEB11206 T6R Figure 7-15 Block Diagram of Core Timer T6 in Timer Mode 7.1.2.2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer mode using the same options for the timer frequencies and the count signal as the core timer T6. In addition to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The individual configuration for timer T5 is determined by its bit-addressable control register T5CON. Note that functions present in both timers of timer block 2 are controlled in the same bit positions and manner in each of the specific control registers. Run control for auxiliary timer T5 can be handled by the associated Run Control Bit T5R in register T5CON. Alternatively, a remote control option (T5RC is set) may be enabled to start and stop T5 via the run bit T6R of core timer T6. Note: The auxiliary timer has no overflow/underflow toggle latch. Therefore, an output line for Overflow/Underflow monitoring is not provided. Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6. The description and the table apply accordingly. Timer T5 in Timer Mode When the auxiliary timer T5 is programmed to timer mode its operation is the same as described for the core timer T6. The descriptions, figures and tables apply accordingly with one exception: * Overflow/Underflow monitoring is not supported (no output toggle latch). Users Manual 7 - 21 2000-06-15 SDA 6000 Peripherals 7.1.2.3 Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer. Depending on which transition of T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit timer/counter. * 32-bit Timer/Counter: If both positive and negative transitions of T6OTL are used to clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core timer T6. Thus, the two timers form a 32-bit timer. * 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer + T6OTL + 16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. In this case T6 can operate in timer, gated timer or counter mode. BPS2 TyI f hw_clk 2n : 1 TyR Core Timer Ty Up/Down TyOTL *) Edge Select Interrupt Request TyOFL Auxiliary Timer Tx TxR Up/Down TxIR Interrupt Request x=5 y=6 UES11207 TxI Note: Line `*' is only affected by over/underflows of T6, but NOT by software modifications of T6OTL. Figure 7-16 Concatenation of Core Timer T6 and Auxiliary Timer T5 Capture/Reload Register CAPREL in Capture Mode This 16-bit register can be used as a capture register for the auxiliary timer T5. This mode is selected by setting bit T5SC in control register T5CON. The CT3 bit selects the external input line CAPIN or the input lines of timer T3 as the source for a capture trigger. Either a positive, a negative, or both a positive and a negative transition at line CAPIN can be selected to trigger the capture function, or transitions on input T3IN or input Users Manual 7 - 22 2000-06-15 SDA 6000 Peripherals T3EUD or both inputs T3IN and T3EUD. The active edge is controlled by bit field CI in register T5CON. The maximum input frequency for the capture trigger signal at CAPIN is fhw_clk/2 (BPS2 = `01'). To ensure that a transition of the capture trigger signal is correctly recognized, its level should be held for at least 2 fhw_clk cycles (BPS2 = `01') before it changes. When the timer T3 capture trigger is enabled (CT3 is set), register CAPREL captures the contents of T5 when transitions of the selected input(s) occur. These values can be used to measure T3's input signals. This is useful e.g. when T3 operates in incremental interface mode, in order to derive dynamic information (speed acceleration) from the input signals. When a selected transition at the external input line CAPIN is detected, the contents of the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR is set. At the same time, timer T5 can be cleared to 0000H. This option is controlled by bit T5CLR in register T5CON. If T5CLR = `0', the contents of timer T5 are not affected by a capture. If T5CLR = `1', timer T5 is cleared after the current timer value has been latched into register CAPREL. Note: Bit T5SC only controls whether a capture is performed or not. If T5SC = `0', the input line CAPIN can still be used to clear timer T5 or as an external interrupt input. This interrupt is controlled by the CAPREL interrupt control register CRIC. Up/Down Input Clock Edge Select CAPIN MUX T3IN/ T3EUD CT3 CI CAPREL Register T5SC Interrupt Request T5CLR T5CC Interrupt Request Auxiliary Timer T5 UEB11208 Figure 7-17 Timer Block 2 Register CAPREL in Capture Mode Users Manual 7 - 23 2000-06-15 SDA 6000 Peripherals Timer Block 2 Capture/Reload Register CAPREL in Reload Mode This 16-bit register can be used as a reload register for the core timer T6. This mode is selected by setting bit T6SR = `1' in register T6CON. The operation causing a reload in this mode is an overflow or underflow of the core timer T6. When timer T6 overflows from FFFFH to 0000H (when counting up) or when it underflows from 0000H to FFFFH (when counting down), the value stored in register CAPREL is loaded into timer T6. This will not set the interrupt request flag CRIR associated with the CAPREL register. However, interrupt request flag T6IR will be set indicating the overflow/underflow of T6. CAPREL Register T6SR Input Clock Core Timer T6 Interrupt Request T6OFL UEB11209 Up/Down Figure 7-18 Timer Block 2 Register CAPREL in Reload Mode Timer Block 2 Capture/Reload Register CAPREL in Capture-And-Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, by setting both bits the two functions can be enabled simultaneously. This feature can be used to generate an output frequency that is a multiple of the input frequency. Users Manual 7 - 24 2000-06-15 SDA 6000 Peripherals Up/Down Input Clock Edge Select CAPIN MUX T3IN/ T3EUD CT3 CI CAPREL Register T6CLR T5SC Interrupt Request T5CLR T5CC Interrupt Request Auxiliary Timer T5 T6SR Input Clock Core Timer T6 Interrupt Request T6OFL UEB11210 Up/Down Figure 7-19 Timer Block 2 Register CAPREL in Capture-And-Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically, but where a finer resolution, i.e. more `ticks' within the time between two external events, is required. For this purpose, the time between the external operations is measured using timer T5 and the CAPREL register. Timer T5 runs in timer mode counting up with a frequency of e.g. fhw_clk/32. The external operations are applied to line CAPIN. When an external operation occurs, the timer T5 contents are latched into register CAPREL, and timer T5 is cleared (T5CLR = `1'). Thus, register CAPREL always contains the correct time between two operations, measured in timer T5 increments. Timer T6, which runs in timer mode counting down with a frequency of e.g. fhw_clk/4, uses the value in register CAPREL to perform a reload on underflow. This means that the value in register CAPREL represents the time between two underflows of timer T6, now measured in timer T6 increments. Since timer T6 runs 8 times faster than timer T5, it will underflow 8 times within the time between two external operations. Thus, the underflow signal of timer T6 generates 8 `ticks'. Upon each underflow, the interrupt request flag T6IR will be set and Users Manual 7 - 25 2000-06-15 SDA 6000 Peripherals bit T6OTL will be toggled. This signal has 8 times more transitions than the signal which is applied to line CAPIN. A certain deviation of the output frequency is generated by the fact that timer T5 will count actual time units (e.g. T5 running at 1 MHz will capture the value 64H/100D for a 10 KHz input signal) while T6OTL will only toggle on an underflow of T6 (i.e. the transition from 0000H to FFFFH). In the above mentioned example, T6 would count down from 64H so the underflow would occur after 101 T6 timing ticks. The actual output frequency then is 79.2 KHz instead of the expected 80 KHz. This can be solved by activating the capture correction (T5CC = `1'). If the capture correction is actived the content of T5 is decremented by 1 before being captured. The deviation described is eliminated (in the example T5 would capture 63H/99D and the output frequency would be 80 KHz). The underflow signal of timer T6 can furthermore be used to clock one or more of the CAPCOM unit's timers, which gives the user the possibility to set compare operations based on a finer resolution than that of the external operations. This connection is accomplished through the T6OFL signal. 7.1.3 GPT Registers All available kernel registers are summarized in Table 7-8. Table 7-8 Name T2CON T3CON T4CON T5CON T6CON CAPREL T2 T3 T4 T5 T6 GPT Register Summary Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Description Timer 2 Control Register Timer 3 Control Register Timer 4 Control Register Timer 5 Control Register Timer 6 Control Register Capture/Reload Register Timer 2 Register Timer 3 Register Timer 4 Register Timer 5 Register Timer 6 Register Function Control Registers The operating mode of the core timer T3 is configured and controlled by its bit-addressable control register T3CON. Users Manual 7 - 26 2000-06-15 SDA 6000 Peripherals T3CON Timer 3 Control Register 15 T3 RDI R 14 T3 CH DIR 13 T3 EDG E 12 11 10 T3 OTL 9 T3 OE 8 T3 UDE 7 T3 UD 6 T3R 5 4 T3M 3 2 1 T3I 0 T3 BPS1 rh rwh rwh rw rwh rw rw rw rw rw rw Field T3I Bits [2:0] Type Description rw Timer 3 Input Parameter Selection Timer mode see Table 7-9 for encoding Gated Timer see Table 7-9 for encoding Counter mode see Table 7-10 for encoding Incremental Interface mode see Table 7-11 for encoding Timer 3 Mode Control 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reserved. Do not use this combination! 101 Reserved. Do not use this combination! 110 Incremental Interface Mode (Rotation detection) 111 Incremental Interface Mode (Edge detection) Timer 3 Run Bit 0 Timer/Counter 3 stops 1 Timer/Counter 3 runs Timer 3 Up/Down Control (when T3UDE = `0') 0 Counting `Up' 1 Counting `Down' Timer 3 External Up/Down Enable 0 Counting direction is internally controlled by SW 1 Counting direction is externally controlled by line T3EUD T3M [5:3] rw T3R [6] rw T3UD [7] rw T3UDE [8] rw Users Manual 7 - 27 2000-06-15 SDA 6000 Peripherals Field T3OE Bits [9] Type Description rw Overflow/Underflow Output Enable 0 T3 overflow/underflow can not be externally monitored 1 T3 overflow/underflow may be externally monitored via T3OUT Timer 3 Output Toggle Latch Toggles on each overflow/underflow of T3. Can be set or reset by software. Timer Block Prescaler 1 The maximum input frequency 00 For Timer 2/3/4 is fhw_clk/8 01 For Timer 2/3/4 is fhw_clk/4 10 For Timer 2/3/4 is fhw_clk/32 11 For Timer 2/3/4 is fhw_clk/16 Timer 3 Edge Detection The bit is set on each successful edge detection. The bit has to be reset by SW. 0 No count edge was detected 1 A count edge was detected Timer 3 Count Direction Change The bit is set on a change of the count direction of timer 3. The bit has to be reset by SW. 0 No change in count direction was detected 1 A change in count direction was detected Timer 3 Rotation Direction 0 Timer 3 counts up 1 Timer 3 counts down T3OTL [10] rwh BPS1 [12:11] rw T3EDGE [13] rwh T3CHDIR [14] rwh T3RDIR [15] rh Users Manual 7 - 28 2000-06-15 SDA 6000 Peripherals Table 7-9 T3I Timer 3 Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for fhw_clk (BPS1 = 00) 000 001 010 011 100 101 110 111 8 16 32 64 128 256 512 1024 fhw_clk (BPS1 = 01) 4 8 16 32 64 128 256 512 fhw_clk (BPS1 = 10) 32 64 128 256 512 1024 2048 4096 fhw_clk (BPS1 = 11) 16 32 64 128 256 512 1024 2048 Table 7-10 T3I 000 001 010 011 1XX Timer 3 Input Parameter Selection for Counter Mode Triggering Edge for Counter Update None. Counter T3 is disabled Positive transition (raising edge) on T3IN Negative transition (falling edge) on T3IN Any transition (raising or falling edge) on T3IN Reserved. Do not use this combination! Table 7-11 T3I 000 001 010 011 1XX Timer 3 Input Parameter Selection for Incremental Interface Mode Triggering Edge for Counter Update None. Counter T3 stops Any transition (raising or falling edge) on T3IN Any transition (raising or falling edge) on T3EUD Any transition (raising or falling edge) on T3IN or T3EUD Reserved. Do not use this combination! Users Manual 7 - 29 2000-06-15 SDA 6000 Peripherals T2CON T4CON Timer 2/4 Control Register 15 Tx RDIR 14 Tx CH DIR 13 Tx EDG E 12 Tx IR DIS 11 0 10 9 Tx RC 8 Tx UDE 7 Tx UD 6 TxR 5 4 TxM 3 2 1 TxI 0 rh rwh rwh rw r rw rw rw rw rw rw Field TxI Bits [2:0] Type Description rw Timer x Input Parameter Selection Timer mode see Table 7-12 for encoding Gated Timer see Table 7-12 for encoding Counter mode see Table 7-13 for encoding Incremental Interface mode see Table 7-14 for encoding Timer x Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Reserved. Do not use this combination! 110 Incremental Interface Mode (Rotation detection) 111 Incremental Interface Mode (Edge detection) Timer x Run Bit 0 Timer/Counter x stops 1 Timer/Counter x runs Timer x Up/Down Control (when TxUDE = `0') 0 Counting `Up' 1 Counting `Down' Timer x External Up/Down Enable 0 Counting direction is internally controlled by SW 1 Counting direction is externally controlled by line TxEUD TxM [5:3] rw TxR [6] rw TxUD [7] rw TxUDE [8] rw Users Manual 7 - 30 2000-06-15 SDA 6000 Peripherals Field TxRC Bits [9] Type Description rw Timer x Remote Control 0 Timer/Counter x is controlled by its own run bit TxR 1 Timer/Counter x is controlled by the run bit of core timer 3 Timer x Interrupt Disable 0 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is enabled 1 Interrupt generation for TxCHDIR and TxEDGE interrupts in Incremental Interface Mode is disabled Timer x Edge Detection The bit is set on each successful edge detection. The bit has to be reset by SW. 0 No count edge was detected 1 A count edge was detected Timer x Count Direction Change The bit is set on a change of the count direction of timer x. The bit has to be reset by SW. 0 No change in count direction was detected 1 A change in count direction was detected Timer x Rotation Direction 0 Timer x counts up 1 Timer x counts down TxIRDIS [12] rw TxEDGE [13] rwh TxCHDIR [14] rwh TxRDIR [15] rh Users Manual 7 - 31 2000-06-15 SDA 6000 Peripherals Table 7-12 T3I Timer x Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for fhw_clk (BPS1 = 00) 000 001 010 011 100 101 110 111 8 16 32 64 128 256 512 1024 fhw_clk (BPS1 = 01) 4 8 16 32 64 128 256 512 fhw_clk (BPS1 = 10) 32 64 128 256 512 1024 2048 4096 fhw_clk (BPS1 = 11) 16 32 64 128 256 512 1024 2048 Table 7-13 TxI X00 001 010 011 101 110 111 Timer x Input Parameter Selection for Counter Mode Triggering Edge for Counter Update None. Counter Tx is disabled Positive transition (raising edge) on TxIN Negative transition (falling edge) on TxIN Any transition (raising or falling edge) on TxIN Positive transition (rising edge) of output toggle latch T3OTL Negative transition (falling edge) of output toggle latch T3OTL Any transition (rising or falling edge) of output toggle latch T3OTL Table 7-14 TxI 000 001 010 011 1XX Timer x Input Parameter Selection for Incremental Interface Mode Triggering Edge for Counter Update None. Counter Tx stops Any transition (raising or falling edge) on TxIN Any transition (raising or falling edge) on TxEUD Any transition (raising or falling edge) on TxIN or TxEUD Reserved. Do not use this combination! Users Manual 7 - 32 2000-06-15 SDA 6000 Peripherals T6CON Timer 6 Control Register 15 T6 SR 14 T6 CLR 13 0 12 11 10 T6 OTL 9 0 8 0 7 T6 UD 6 T6R 5 4 T6M 3 2 1 T6I 0 BPS2 rw rw r rw rwh rw rw rw rw rw rw Field T6I T6M Bits [2:0] [5:3] Type Description rw rw Timer 6 Input Parameter Selection Timer mode see Table 7-15 for encoding Timer 6 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Reserved. Do not use this combination! 010 Reserved. Do not use this combination! 011 Reserved. Do not use this combination! 1XX Reserved. Do not use this combination! Timer 6 Run Bit 0 Timer/Counter 6 stops 1 Timer/Counter 6 runs Timer 6 Up/Down Control 0 Counting `Up' 1 Counting `Down' Timer 6 Output Toggle Latch Toggles on each overflow/underflow of T6. Can be set or reset by software. Timer Block Prescaler 2 The maximum input frequency 00 For Timer 5/6 is fhw_clk/4 01 For Timer 5/6 is fhw_clk/2 10 For Timer 5/6 is fhw_clk/16 11 For Timer 5/6 is fhw_clk/8 Timer 6 Clear Bit 0 Timer 6 is not cleared on a capture event 1 Timer 6 is cleared on a capture event Timer 6 Reload Mode Enable 0 Reload from register CAPREL disabled 1 Reload from register CAPREL enabled T6R [6] rw T6UD [7] rw T6OTL [10] rwh BPS2 [12:11] rw T6CLR [14] rw T6SR [15] rw Users Manual 7 - 33 2000-06-15 SDA 6000 Peripherals Table 7-15 T6I Timer 6 Input Parameter Selection for Timer Mode and Gated Mode Prescaler for Prescaler for Prescaler for Prescaler for fhw_clk (BPS2 = 00) fhw_clk (BPS2 = 01) fhw_clk (BPS2 = 10) fhw_clk (BPS2 = 11) 2 4 8 16 32 64 128 256 16 32 64 128 256 512 1024 2048 8 16 32 64 128 256 512 1024 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 512 Table 7-16 T6I 000 001 010 011 1XX Timer 6 Input Parameter Selection for Counter Mode Triggering Edge for Counter Update None. Counter T6 is disabled Reserved. Do not use this combination! Reserved. Do not use this combination! Reserved. Do not use this combination! Reserved. Do not use this combination! Users Manual 7 - 34 2000-06-15 SDA 6000 Peripherals T5CON Timer 5 Control Register 15 T5 SR 14 T5 CLR 13 CI 12 11 T5 CC 10 CT3 9 T5 RC 8 0 7 T5 UD 6 T5R 5 4 T5M 3 2 1 T5I 0 rw rw rw rw rw rw rw rw rw rw rw Field T5I Bits [2:0] Type Description rw Timer 5 Input Parameter Selection Timer mode see Table 7-17 for encoding Counter mode see Table 7-18 for encoding Timer 5 Mode Control (Basic Operating Mode) 000 Timer Mode 001 Counter Mode 010 Reserved. Do not use this combination! 011 Reserved. Do not use this combination! 1XX Reserved. Do not use this combination! Timer 5 Run Bit 0 Timer/Counter 5 stops 1 Timer/Counter 5 runs Timer 5 Up/Down Control 0 Counting `Up' 1 Counting `Down' Timer 5 Remote Control 0 Timer/Counter x is controlled by its own run bit T5R 1 Timer/Counter 5 is controlled by the run bit of core timer 6 Timer 3 Capture Trigger Enable 0 Capture trigger from input line CAPIN 1 Capture trigger from T3 input lines Timer 5 Capture Correction 0 T5 is just captured without any correction 1 T5 is decremented by 1 before being captured T5M [5:3] rw T5R [6] rw T5UD [7] rw T5RC [9] rw CT3 [10] rw T5CC [11] rw Users Manual 7 - 35 2000-06-15 SDA 6000 Peripherals Field CI Bits Type Description Register CAPREL Capture Trigger Selection (depending in bit CT3) 00 Capture disabled 01 Positive transition (rising edge) on CAPIN or any transition on T3IN 10 Negative transition (falling edge) on CAPIN or any transition on T3EUD 11 Any transition (rising or falling edge) on CAPIN or any transition on T3IN or T3EUD Timer 5 Clear Bit 0 Timer 5 is not cleared on a capture operation 1 Timer 5 is cleared on a capture operation Timer 5 Capture Mode Enable 0 Capture into register CAPREL disabled 1 Capture into register CAPREL enabled [13:12] rw T5CLR [14] rw T5SC [15] rw Table 7-17 Timer 5 Input Parameter Selection for Timer Mode and Gated Mode T5I Prescaler for Prescaler for Prescaler for Prescaler for fhw_clk (BPS2 = 00) fhw_clk (BPS2 = 01) fhw_clk (BPS2 = 10) fhw_clk (BPS2 = 11) 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 512 2 4 8 16 32 64 128 256 16 32 64 128 256 512 1024 2048 8 16 32 64 128 256 512 1024 Users Manual 7 - 36 2000-06-15 SDA 6000 Peripherals Table 7-18 T5I X00 001 010 011 101 110 111 Timer 5 Input Parameter Selection for Counter Mode Triggering Edge for Counter Update None. Counter T5 is disabled Reserved. Do not use this combination. Reserved. Do not use this combination. Reserved. Do not use this combination. Positive transition (rising edge) of output toggle latch T6OTL Negative transition (falling edge) of output toggle latch T6OTL Any transition (rising or falling edge) of output toggle latch T6OTL 7.1.4 Interrupts For a detailed description of the various interrupts see description above. An overview is given with a Table 7-19: . Table 7-19 Interrupt Timer 2 Overflow Timer 2 Underflow Timer 3 Overflow Timer 3 Underflow Timer 4 Overflow Timer 4 Underflow Timer 5 Overflow Timer 5 Underflow Timer 6 Overflow Timer 6 Underflow Users Manual Peripheral Name Interrupt Sources Interrupt Node T2IC T2IC T3IC T3IC T4IC T4IC T5IC T5IC T6IC T6IC Description Interrupt is requested on overflow of timer 2 if counting up. Interrupt is requested on underflow of timer 2 if counting down. Interrupt is requested on overflow of timer 3 if counting up. Interrupt is requested on underflow of timer 3 if counting down. Interrupt is requested on overflow of timer 4 if counting up. Interrupt is requested on underflow of timer 4 if counting down. Interrupt is requested on overflow of timer 5 if counting up. Interrupt is requested on underflow of timer 5 if counting down. Interrupt is requested on overflow of timer 6 if counting up. Interrupt is requested on underflow of timer 6 if counting down. 7 - 37 2000-06-15 SDA 6000 Peripherals Table 7-19 Interrupt Peripheral Name Interrupt Sources (cont'd) Interrupt Node Description Interrupt is requested on a change of the count direction in the Incremental Interface Mode (T2I = 110). Interrupt is requested on a successful detected edge resulting in a timer count action (T2I = 111). Interrupt is requested on a change of the count direction in the Incremental Interface Mode (T3I = 110). Interrupt is requested on a successful detected edge resulting in a timer count action (T3I = 111). Interrupt is requested on a change of the count direction in the Incremental Interface Mode (T4I = 110). Interrupt is requested on a successful detected edge resulting in a timer count action (T4I = 111). Interrupt is requested on a trigger signal for reloading timer 3 in Reload Mode (T2I = 100). Interrupt is requested on a trigger signal for reloading timer 3 in Reload Mode (T4I = 100). Interrupt is requested on a trigger signal for a capture action to capture timer 3 in timer 2 Capture Mode (T2I = 101). Interrupt is requested on a trigger signal for a capture action to capture timer 3 in timer 4 Capture Mode (T4I = 101). Interrupt is requested on a trigger signal for a capture action of timer 5 to register CAPREL in Capture Mode (T5SC = 1). Rotation T2IC Direction Change Timer 2 Edge Detection T2IC Timer 2 Rotation T3IC Direction Change Timer 3 Edge Detection T3IC Timer 3 Rotation T4IC Direction Change Timer 4 Edge Detection T4IC Timer 4 Reload Action Timer 2 Reload Action Timer 4 Capture Action Timer 2 Capture Action Timer 4 Capture Action Timer Block 2 T2IC T4IC T2IC T4IC CRIC Users Manual 7 - 38 2000-06-15 SDA 6000 Peripherals 7.2 7.2.1 Real-time Clock General Description The Real Time Clock (RTC) module of M2 is basically an independent timer chain and counts time ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can work fully asynchronous to the system frequency (33.33 MHz) and is optimized on a low power consumption. The RTC serves different purposes: * * * * Real-time clock to determine the current time and date Cyclic time based interrupt Alarm interrupt for wake up on a defined time 48-bit timer for long term measurements The real time clock module provides three different types of registers: a control register for controlling the RTCs functionality, three data registers for setting the clock divider for RTC base frequency programming and for flexible interrupt generation, and three counter registers that contain the actual time and date. The interrupts are programmed via one interrupt subnode register and via an interrupt node register. Control Registers Data Registers Counter Registers Interrupt Control RTCCON T14REL RTCRELH RTCRELL T14 RTCH RTCL RTCISNC RTCCON T14REL T14 RTCRELH RTCRELL RTC Control Register Timer T14 Reload Register Timer T14 Count Register RTC Timer Reload Register, High Word RTC Timer Reload Register, Low Word RTC Timer Count Register, High Word RTCH RTC Timer Count Register, Low Word RTCL RTCISNC RTC Interrupt Sub Node Control Register UEA11139 Figure 7-20 RTC Register Overview The RTC module consists of a chain of 2 divider blocks, the reloadable 16-bit timer T14 and the 32-bit RTC timer (accessible via registers RTCH and RTCL). Both timers count up. Timer T14 is reloaded with the value of register T14REL on every T14 timer overflow. T14REL is transparent during reload state. Figure 7-21 shows the RTC block diagram: Users Manual 7 - 39 2000-06-15 SDA 6000 Peripherals 3 MHz RTCR RTC_T14INT Interrupt Subnode RTC1INT RTCRELL1 6 Bit RTC2INT RTCREL2 6 Bit RTC_INT RTC0INT RTCRELL0 T14REL(16 Bit) 10 Bit RTC3INT RTCREL3 10 Bit T14_IN T14(16 Bit) 10 Bit RTCL0 6 Bit RTCL1 6 Bit RTCH2 10 Bit RTCH3 UEB11140 Figure 7-21 RTC Block Diagram RTC Control The operating behavior of the RTC module is controlled by the RTCCON register. The RTC starts counting by setting the RTCR run bit. After reset, the run bit is set and the RTC automatically starts operation. Setting bits T14DEC or T14INC allows the T14 timer to be manually and asynchronously decremented or incremented. These bits are cleared by hardware after the decrement/increment operation. The RTC is only reset in case of a hardware reset, so it keeps on running during idle and sleep mode. Cyclic Interrupt Generation The RTC module can generate an interrupt request RTC_INT whenever timer T14 overflows and is reloaded. This interrupt request may be used, for example, to provide a system time tick, independent of the CPU clock frequency, without loading the general purpose timers, or to wake up regularly from idle mode. The T14 overflow interrupt (RTC_T14INT) cycle time can be adjusted via the timer T14 reload register T14REL. The 32 bit timer (RTCL and RTCH) can be divided into smaller reloadable timers. Each sub-timer can be programmed for an overflow on different time bases (e.g. second, hour, minute, day). With each timer overflow an RTC interrupt is generated. All these RTC interrupts are ored within the RTC module via the interrupt subnode RTCISNC to one interrupt request RTC_INT. This interrupt RTC_INT is one source of another interrupt subnode ISNC in the interrupt controller. The other interrupt input of subnode ISNC is disconnected in the M2. With typical values of T14REL = F448H, RTCRELL = 1018H and Users Manual 7 - 40 2000-06-15 SDA 6000 Peripherals RTCRELH = FA04H, counter T14 generates one overflow per millisecond, RTCL0 one per second, RTCL1 one per minute, RTCH2 one per hour and RTCH3 one per day. 48-bit Timer Operation The concatenation of the 16-bit reload timer T14 and the 32-bit RTC timer can be regarded as a 48-bit timer which counts with the RTC count input frequency (3 MHz). The reload registers T14REL, RTCRELL and RTCRELH should be cleared to get a 48-bit binary timer. However, any other reload values may be used. Interrupt Subnode RTCISNC All RTC interrupts are connected to one interrupt node via an interrupt subnode. For this interrupt sharing each interrupt source has, in addition to the node enable and request flag its own enable and request flag located in register RTCISNC. After an RTC interrupt (RTC_INT) is arbitrated, the interrupt service routine has to check all the enabled sources request flags and run the respective software routine. The request flags have to be deleted by software before leaving the interrupt service routine. Reset Behavior The RTC registers are only cleared or set by a hardware reset. Bit RTCR is set when the hardware is reset. 7.2.2 RTCCON 15 - Register Description Reset Value: 0003H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 T14 INC 2 T14 DEC 1 0 0 RTC R rw Bit RTCR Function RTC Run Bit `0': RTC stops `1': RTC runs rw rw T14DEC Decrement T14 Timer Value Setting this bit to 1 effects a decrement of the T14 timer value. The bit is cleared by hardware after decrementation. Increment T14 Timer Value Setting this bit to 1 effects an increment of the T14 timer value. The bit is cleared by hardware after incrementation. 7 - 41 2000-06-15 T14INC Users Manual SDA 6000 Peripherals Note: Bit RTCR is set on hardware reset. T14 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 TIMER14(15 ..0 ) rw Bit TIMER14 (15 ... 0) Function 16 Bit Timer Register Timer T14 generates the input clock for the RTC register and the periodic interrupt. Reset Value: 0000H 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T14REL 15 14 TIMER14REL(15 ..0 ) rw Bit TIMERREL14 (15 ... 0) RTCL 15 14 13 Function 16 Bit Reload Register for Timer 14 Represents the 16 bit reload value for T14 Reset Value: 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCL1(5 .. 0) RTCL0(9 .. 0) rw Bit RTCL1 (5 ... 0) RTCL0 (9 ... 0) Function Low Word of 32 Bit Capture Register. Users Manual 7 - 42 2000-06-15 SDA 6000 Peripherals RTCH 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000 H 3 2 1 0 RTCH3(9.. 0) RTCH2(5 .. 0) rw Bit RTCH3 (9 ... 0) RTCH2 (5 ... 0) RTCRELL 15 14 13 Function High Word of 32 Bit Capture Register. Reset Value: 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCRELL1(5 .. 0) RTCRELL0(9 .. 0) rw Bit RTCRELL1 (5 ... 0) RTCRELL0 (9 ... 0) RTCRELH 15 14 13 Function Low Word of 32 Bit Reload Register. Reset Value: 0000H 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCRELH3(9.. 0) RTCRELH2(5 .. 0) rw Bit RTCRELH2 (5 ... 0) RTCRELH3 (9 ... 0) Users Manual Function High Word of 32 Bit Reload Register. 7 - 43 2000-06-15 SDA 6000 Peripherals RTC Interrupt Subnode Control RTCISNC 15 - Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 RTC 3 IR 8 RTC 3IE 7 RTC 2 IR 6 RTC 2IE 5 RTC 1 IR 4 RTC 1 IE 3 RTC 0 IR 2 RTC 0IE 1 T14 IR 0 T14 IE rw rw rw rw rw rw rw rw rw rw Bit T14IR Function T14 Overflow Interrupt Request Flag `0': No request pending. `1': This source has raised an interrupt request. T14 Overflow Interrupt Enable Control Bit `0': Interrupt request is disabled. `1': Interrupt request is enabled. RTCx Interrupt Request Flag `0': No request pending. `1': This source has raised an interrupt request. RTCx Interrupt Enable Control Bit `0': Interrupt request is disabled. `1': Interrupt request is enabled. T14IE RTCxIR RTCxIE Users Manual 7 - 44 2000-06-15 SDA 6000 Peripherals ISNC 15 - Reset Value: 0000H 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 INT2 IE 2 INT2 IR 1 RTC INT IE 0 RTC INT IR rw rw rw rw Bit RTCINTIR Function RTC Interrupt Request Flag `0': No request pending. `1': RTC has raised an interrupt request. RTC Interrupt Enable Control Bit `0': Interrupt request is disabled. `1': Interrupt request is enabled. Interrupt Request Flag of 2nd Source disconnected in M2. 2nd Source Interrupt Enable Control Bit `0': recommended value. RTCINTIE INT2IR INT2IE Note: The interrupt request flags of both RTC interrupt subnodes have to be cleared by software inside the interrupt service routine. Users Manual 7 - 45 2000-06-15 SDA 6000 Peripherals 7.3 Asynchronous/Synchronous Serial Interface The Asynchronous/Synchronous Serial Interface ASC0 provides serial communication between M2 and other microcontrollers, microprocessors or external peripherals. It provides the following features: * Full duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baud rate from 2.0625 MBaud to 0.48 Baud (@ 33 MHz clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability * Support for IrDA data transmission/reception up to max. 115.2 KBaud * Autobaud detection unit for asynchronous operating modes - Detection of standard baud rates 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400 Baud - Detection of non-standard baud rates - Detection of asynchronous modes 7 bit, even parity; 7 bit, odd parity; 8 bit, even parity; 8 bit, odd parity; 8 bit, no parity - Automatic initialization of control bits and baud rate generator after detection - Detection of a serial two-byte ASCII character frame * Half-duplex 8-bit synchronous operating mode - Baud rate from 4.125 MBaud to 420 Baud (@ 33 MHz clock) * Double buffered transmitter/receiver * Interrupt generation - on a transmitter buffer empty condition - on a transmit last bit of a frame condition - on a receiver buffer full condition - on an error condition (frame, parity, overrun error) - on the start and the end of a autobaud detection Figure 7-22 shows a block diagram of the ASC with its operating modes (asynchronous and synchronous mode.) Users Manual 7 - 46 2000-06-15 SDA 6000 Peripherals . Asynchronous Mode Prescaler/ Fractional Divider 33 MHz fDIV Baud Rate Timer Autobaud Detection Serial Port Control RxD IrDA Decoding Synchronous Mode MUX Receive/Transmit Buffers and Shift Registers IrDA Coding MUX TxD fMOD /2 or /3 Baud Rate Timer Serial Port Control TxD Shift Clock Receive/Transmit Buffers and Shift Registers RxDO RxDI Note: RxDI and RxDO are concatenated in the port logic to pin RxD. UEB11141 Figure 7-22 Block Diagram of the ASC0 Users Manual 7 - 47 2000-06-15 SDA 6000 Peripherals Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ODP3 DP3 P3 RxD0/P3.11 TxD0/P3.10 ODP3 DP3 S0BG S0TBUF S0TIC S0TBIC ABCON ABSTAT S0BG S0TBUF S0RBUF S0CON S0FDV S0PMW ABCON ABSTAT S0TIC S0RIC S0EIC S0TBIC Port 3 Open Drain Control Register Port 3 Direction Control Register ASC0 Baud Rate Generator/Reload Register ASC0 Transmit Buffer Register ASC0 Transmit Interrupt Control Register ASC0 Transmit Buffer Interrupt Control Register Autobaud Control Register Autobaud Status Register P3 S0CON S0FDV S0PMW S0RBUF S0RIC S0EIC Port 3 Data Register ASC0 Control Register ASC0 Fractional Divider Regiser ASC0 IrDA Pulse Mode and Width Register ASC0 Receive Buffer Register (read only) ASC0 Receive Interrupt Control Register ASC0 Error Interrupt Control Register UEA11142 Figure 7-23 ASC Register Overview The ASC0 supports full-duplex asynchronous communication up to 2.08 MBaud and half-duplex synchronous communication up to 4.16 MBaud (@ 33.33 MHz CPU clock). In synchronous mode, data is transmitted or received synchronous to a shift clock which is generated by the microcontroller. In asynchronous mode, 8- or 9-bit data transfer, parity generation, and the number of stop bits can be selected. Parity, framing, and overrun error detection is provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism to distinguish address from data bytes is included. Testing is supported by a loop-back option. A 13-bit baud rate timer with a versatile input clock divider circuitry provides the ASC0 with the serial clock signal. In a special asynchronous mode, the ASC0 supports IrDA data transmission up to 115.2 KBaud with fixed or programmable IrDA pulse width. A transmission is started by writing to the Transmit Buffer register S0TBUF (by way of an instruction or a PEC data transfer). Only the number of data bits which is determined by the selected operating mode, will actually be transmitted, e.g. bits written to positions 9 through 15 of register S0TBUF are always insignificant. Data transmission is double-buffered, so a new character may be written to the transmit buffer register, before the transmission of the previous character is complete. This allows the transmission of characters back-to-back without gaps. Users Manual 7 - 48 2000-06-15 SDA 6000 Peripherals Data reception is enabled by the receiver enable bit S0REN. After reception of a character has been completed, the received data and, if provided by the selected operating mode, the received parity bit can be read from the (read-only) receive buffer register S0RBUF. Bits in the upper half of S0RBUF which are not valid in the selected operating mode will be read as zeros. Data reception is double-buffered, so that reception of a second character may begin before the previously received character has been read out of the receive buffer register. In all modes, receive buffer overrun error detection can be selected through bit S0OEN. When enabled, the overrun error status flag S0OE and the error interrupt request line S0EIR will be activated if the receive buffer register has not been read when the reception of a second character is complete. The previously received character in the receive buffer is overwritten. The Loop-Back option (selected by bit S0LB) allows the data currently being transmitted to be received simultaneously in the receive buffer. This may be used to test serial communication routines at an early stage without having to provide an external network. In loop-back mode the alternate input/output functions of the Port 3 pins are not necessary. Note: Serial data transmission or reception is only possible when the baud rate generator run bit S0R is set to `1'. Otherwise the serial interface is idle. Do not program the mode control field S0M in register S0CON to one of the reserved combinations to avoid unpredictable behavior of the serial interface. 7.3.1 Asynchronous Operation Asynchronous mode supports full-duplex communication, where both transmitter and receiver use the same data frame format and the same baud rate. Data is transmitted on pin TXD0 and received on pin RXD0. These signals are alternate functions of Port 3 pins. IrDA data transmission/reception supports up to 115.2 KBit/s. Figure 7-24 shows the block diagram of the ASC0 operating in asynchronous mode. Users Manual 7 - 49 2000-06-15 SDA 6000 Peripherals S0FDE Fractional Divider 33 MHz /2 /3 MUX 13-Bit Reload Register fDIV 13-Bit Baud Rate Timer / 16 fBR S0R S0BRS S0M S0STR S0REN S0FEN S0PEN S0OEN S0LB S0PE S0FE S0OE S0RIR S0TIR Serial Port Control Shift Clock S0TBIR S0EIR Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request Shift Clock MUX Sampling Receive Shift Register Transmit Shift Register IrDA Coding IrDA Decoding Receive Buffer Reg. S0RBUF Transmit Buffer Reg. S0TBUF MUX MUX RxD0 Internal Bus UES11143 TxD0 Figure 7-24 Asynchronous Mode of Serial Channel ASC0 Users Manual 7 - 50 2000-06-15 SDA 6000 Peripherals 7.3.1.1 Asynchronous Data Frames 8-Bit Data Frames 8-bit data frames either consist of 8 data bits D7 ... D0 (S0M = `001B'), or of 7 data bits D6 ... D0 plus an automatically generated parity bit (S0M = `011B'). Parity may be odd or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the 7 data bits is `1'. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 8-bit data mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.7. 10-/11-Bit UART Frame 0 SOM = 001 B Start Bit D0 LSB D1 D2 D3 8 Data Bits D6 D7 MSB 1 D5 (1st) Stop Bit 1 (2nd) Stop Bit D4 10-/11-Bit UART Frame 0 SOM = 011 B Start Bit D0 LSB D1 D2 D3 7 Data Bits D6 MSB Parity Bit 1 D5 (1st) Stop Bit 1 (2nd) Stop Bit UED11144 D4 Figure 7-25 Asynchronous 8-Bit Frames 9-Bit Data Frames 9-bit data frames either consist of 9 data bits D8 ... D0 (S0M = `100B'), of 8 data bits D7 ... D0 plus an automatically generated parity bit (S0M = `111B') or of 8 data bits D7 ... D0 plus wake-up bit (S0M = `101B'). Parity may be odd or even, depending on bit S0ODD in register S0CON. An even parity bit will be set, if the modulo-2-sum of the 8 data bits is `1'. An odd parity bit will be cleared in this case. Parity checking is enabled via bit S0PEN (always OFF in 9-bit data and wake-up mode). The parity error flag S0PE will be set along with the error interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.8. Users Manual 7 - 51 2000-06-15 SDA 6000 Peripherals 11-/12-Bit UART Frame 0 Start Bit D0 LSB D1 D2 D3 9 Data Bits 1 D5 D6 D7 Bit 9 (1st) Stop Bit 1 (2nd) Stop Bit D4 SOM = 100 B : Bit 9 = Data Bit D8 SOM = 101 B : Bit 9 = Wake-up Bit SOM = 111 B : Bit 9 = Parity Bit UED11145 Figure 7-26 Asynchronous 9-Bit Frames In wake-up mode, received frames are only transferred to the receive buffer register if the 9th bit (the wake-up bit) is `1'. If this bit is `0', no receive interrupt request will be activated and no data will be transferred. This feature may be used to control communication in a multi-processor system: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the additional 9th bit is a `1' for an address byte and a `0' for a data byte, so no slave will be interrupted by a data `byte'. An address `byte' will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the 8 LSBs of the received character (the address). The addressed slave will switch to 9-bit data mode (e.g. by clearing bit S0M.0), which enables it to also receive further data bytes (having the wake-up bit cleared). The slaves that were not being addressed remain in 8-bit data + wake-up bit mode, ignoring the following data bytes. IrDA Frames The modulation schemes of IrDA is based on standard asynchronous data transmission frames. The asynchronous data format in IrDA mode (S0M = 010B) is defined as follows: * 1 start bit/8 data bits/1 stop bit The coding/decoding of/to the asynchronous data frames is shown in Figure 7-27. In general, during the IrDA transmissions, UART frames are encoded into IR frames and vice versa. A low level on the IR frame indicates a `LED off' state. A high level on the IR frame indicates a `LED on' state. For a `0'-bit in the UART frame, a high pulse is generated. For a `1'-bit in the UART frame, no pulse is generated. The high pulse starts in the middle of a bit cell and has a fixed width of 3/16 of the bit time. The ASC0 also allows the length of the IrDA high pulse to be programmed. Furthermore, the polarity of the received IrDA pulse can be inverted in IrDA mode. Figure 7-27 shows the non-inverted IrDA pulse scheme. Users Manual 7 - 52 2000-06-15 SDA 6000 Peripherals UART Frame Start Bit 0 1 0 1 8 Data Bits 0 0 1 1 0 Stop Bit 1 IR Frame Start Bit 0 Bit Time 1/2 BitTime Pulse Width = 3/16 Bit Time (or variable length) UED11146 8 Data Bits 1 0 1 0 0 1 1 0 Stop Bit 1 Figure 7-27 IrDA Frame Encoding/Decoding 7.3.1.2 Asynchronous Transmission Asynchronous transmission begins at the next overflow of the divide-by-16 baud rate timer (transition of the baud rate clock fBR), if bit S0R must be set and data has been loaded into S0TBUF. The transmitted data frame consists of three basic elements: * the start bit * the data field (8 or 9 bits, LSB first, including a parity bit, if selected) * the delimiter (1 or 2 stop bits) Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request line S0TBIR being activated. S0TBUF may now be loaded with the next data, while transmission of the previous one is still going on. The transmit interrupt request line S0TIR will be activated before the last bit of a frame is transmitted, e.g. before the first or the second stop bit is shifted out of the transmit shift register. For alternate data output the transmitter output pin TXD0 must be configured. Users Manual 7 - 53 2000-06-15 SDA 6000 Peripherals 7.3.1.3 Asynchronous Reception Asynchronous reception is initiated by a falling edge (1-to-0 transition) on pin RXD0, provided that bits S0R and S0REN are set. The receive data input pin RXD0 is sampled at 16 times the rate of the selected baud rate. A majority decision of the 7th, 8th and 9th sample determines the effective bit value. This avoids erroneous results that may be caused by noise. If the detected value is not equal to `0' when the start bit is sampled, the receive circuit is reset and waits for the next 1-to-0 transition at pin RXD0. If the start bit proves valid, the receive circuit continues sampling and shifts the incoming data frame into the receive shift register. When the last stop bit has been received, the content of the receive shift register is transferred to the receive data buffer register S0RBUF. Simultaneously, the receive interrupt request line S0RIR is activated after the 9th sample in the last stop bit time slot (as programmed), regardless whether valid stop bits have been received or not. The receive circuit then waits for the next start bit (1-to-0 transition) at the receive data input pin. The receiver input pin RXD0 must be configured for input. Asynchronous reception is stopped by clearing bit S0REN. A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Start bits that follow this frame will not be recognized. Note: In wake-up mode received frames are only transferred to the receive buffer register, if the 9th bit (the wake-up bit) is equal to `1'. If this bit is equal to `0', no receive interrupt request will be activated and no data transferred. IrDA Mode The duration of the IrDA pulse is normally 3/16 of a bit period. The IrDA standard also allows the pulse duration to be independent of the baud rate or bit period. In this case the transmitted pulse always has the width corresponding to the 3/16 pulse width at 115.2 KBaud which is 1.67 s. Both bit period dependent or fixed IrDA pulse width generation can be selected. The IrDA pulse width mode is selected by bit S0IRPW, which is located in register S0PWM. In case of a fixed IrDA pulse width generation, the lower 8 bits in register S0PWM are used to adapt the IrDA pulse width to a fixed value of e.g. 1.67 s. The fixed IrDA pulse width is generated by a programmable timer as shown in Figure 7-28. Users Manual 7 - 54 2000-06-15 SDA 6000 Peripherals S0PWM Start Timer tIPW 8-Bit Timer IrDA Pulse UED11147 33 MHz Figure 7-28 Fixed IrDA Pulse Generation The IrDA pulse width can be calculated according to the formulas given in the following table. S0PWM 1 ... 255 S0IPWM 0 1 Formulas t IPW = t IPW = 3 16 x 33 MHz S0PWM 33 MHz t IPW min = (S0PWM >> 1) 33 MHz The name S0PWM in the formulas represents the contents of the reload register S0PWM (bits S0PW0-7), taken as an unsigned 8-bit integer. The content of S0PWM further defines the minimum IrDA pulse width (tIPW min) which is still recognized as a valid IrDA pulse during a receive operation. This function is independent of the selected IrDA pulse width mode (fixed or variable) which is defined by bit S0IRPW in register S0PWM. The minimum IrDA pulse width is calculated by a shift right operation of S0PWM bit 7-0 by one bit divided by the CPU clock (33.33 MHz). Note: If S0IRPW=0 (fixed IrDA pulse width), SxPWM bit 7-0 must be loaded with a value which assures that t IPW > t IPW min. RXD/TXD Data Path Selection in Asynchronous Modes The data paths for the serial input and output data in asynchronous modes are affected by several control bits in the registers S0CON and S0ABCON, as shown in Figure 7-29. The synchronous mode operation is not affected by these data path selection capabilities. The input signal from RXD passes an inverter which is controlled by bit ABCON_RXINV. The output signal of this inverter is used for the autobaud detection and may bypass the ASC_P logic in the echo mode (controlled by bit ABCON_ABEM). Furthermore, two multiplexers are in the RXD input signal path to provide the loopback mode capability (controlled by bit CON_LB) and the IrDA receive pulse inversion capability (controlled by bit CON_RXDI). Users Manual 7 - 55 2000-06-15 SDA 6000 Peripherals Depending on the asynchronous operating mode (controlled by bitfield CON_M), the ASC output signal or the RXD input signal in echo mode (controlled by bit ABCON_ABEM) is switched to the TXD output by an inverter (controlled by bit ABCON_TXINV). Autobaud Detection ABCON RXINV ABEM RxD MUX MUX MUX IrDA Coding IrDA Decoding MUX MUX M MUX TxD TXINV ASC Asynch. Mode Logic CON RxDI LB UED11148 Figure 7-29 RXD/TXD Data Path in Asynchronous Modes In echo mode, the transmit output signal of the ASC_P3 logic is blocked by the echo mode output multiplexer. Figure 7-29 also shows that it is not possible to use an IrDA coded receiver input signal for autobaud detection. 7.3.2 Synchronous Operation Synchronous mode supports half-duplex communication, basically for simple I/O expansion via shift registers. Data is transmitted and received via pin RXD0 while pin TXD0 outputs the shift clock. These signals are alternate functions of port pins. Synchronous mode is selected with S0M = `000B'. 8 data bits are transmitted or received synchronous to a shift clock, generated by the internal baud rate generator. The shift clock is only active as long as data bits are transmitted or received. Users Manual 7 - 56 2000-06-15 SDA 6000 Peripherals 13-Bit Reload Register 33 MHz /2 MUX S0R /3 fDIV 13-Bit Baud Rate Timer fBRT /4 fBR S0BRS S0M = 000 B S0OE TxD0 S0REN S0OEN S0LB Shift Clock Serial Port Control Shift Clock S0RIR S0TIR S0TBIR S0EIR Receive Int. Request Transmit Int. Request Transmit Buffer Int. Request Error Int. Request RxD0 0 MUX 1 Receive Shift Register Transmit Shift Register Receive Buffer Reg. S0RBUF Transmit Buffer Reg. S0TBUF Internal Bus UES11149 Figure 7-30 Synchronous Mode of Serial Channel ASC0 7.3.2.1 Synchronous Transmission Synchronous transmission begins within 4 state times after data has been loaded into S0TBUF, provided that S0R is set and S0REN = `0' (half-duplex, no reception). Exception: in loop-back mode (bit S0LB in S0CON set), S0REN must be set to receive the transmitted byte. Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent. This is indicated by the transmit buffer interrupt request line S0TBIR being activated. S0TBUF may now be loaded with the next Users Manual 7 - 57 2000-06-15 SDA 6000 Peripherals data, while transmission of the previous one is still going on. The data bits are transmitted synchronous to the shift clock. After the bit time for the 8th data bit, both pins TXD0 and RXD0 will go high, the transmit interrupt request line S0TIR is activated, and serial data transmission stops. Pin TXD0 must be configured for alternate data output in order to support the shift clock. Pin RXD0 must also be configured for output during transmission. 7.3.2.2 Synchronous Reception Synchronous reception is initiated by setting bit S0REN = `1'. If bit S0R = 1, the data applied at pin RXD0 is clocked into the receive shift register synchronous to the clock which is output at pin TXD0. After the 8th bit has been moved in, the content of the receive shift register is transferred to the receive data buffer S0RBUF, the receive interrupt request line S0RIR is activated, the receiver enable bit S0REN is reset, and serial data reception stops. Pin TXD0 must be configured for alternate data output in order to support the shift clock. Pin RXD0 must be configured as an alternate data input. Synchronous reception is terminated by clearing bit S0REN. A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request, if appropriate. Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission. If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete, both the error interrupt request line S0EIR and the overrun error status flag S0OE will be activated/set, provided the overrun check has been enabled by bit S0OEN. 7.3.2.3 Synchronous Timing Figure 7-31 shows timing diagrams of the ASC0 synchronous mode data reception and data transmission. In idle state the shift clock is at high level. With the beginning of a synchronous transmission of a data byte, the data is shifted out at pin RXD0 with the falling edge of the shift clock. If a data byte is received through pin RXD0, data is latched with the rising edge of the shift clock. Between two consecutive receive or transmit data bytes one shift clock cycle (fBR) delay is inserted. Users Manual 7 - 58 2000-06-15 SDA 6000 Peripherals Receive/Transmit Timing Shift Latch Shift Latch Shift Shift Clock Transmit Data Data Bit n Data Bit n+1 Data Bit n+2 Receive Data Valid Data n Valid Data n+1 Valid Data n+2 Continuous Transmit Timing Shift Clock Transmit Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 1. Byte Receive Data D0 D1 D2 D3 D4 1. Byte D5 D6 D7 D0 D1 2. Byte D2 D3 2. Byte UET11150 Figure 7-31 ASC0 Synchronous Mode Waveforms 7.3.3 Baud Rate Generation The serial channel ASC0 has its own dedicated 13-bit baud rate generator with 13-bit reload capability, allowing baud rate generation to be independent of the GPT timers. The baud rate generator is clocked with the CPU clock. The baud rate timer is counting downwards and can be started or stopped through the baud rate generator run bit S0R in register S0CON. Each underflow of the timer provides one clock pulse to the serial channel. The timer is reloaded with the value stored in its 13-bit reload register each time it underflows. The resulting clock fBRT is again divided according to the operating mode and controlled by the baud rate selection bit S0BRS. If S0BRS = `1', the clock signal is additionally divided to 2/3rd of its frequency (see formulas and table). So the baud rate of ASC0 is determined by the CPU clock, the reload value, the value of S0BRS and the operating mode (asynchronous or synchronous). Users Manual 7 - 59 2000-06-15 SDA 6000 Peripherals Register S0BG is the dual-function Baud Rate Generator/Reload register. Reading S0BG returns the content of the timer (bits 15 ... 13 return zero), while writing to S0BG always updates the reload register (bits 15 ... 13 are insignificant). An auto-reload of the timer with the content of the reload register is performed each time S0BG is written to. However, if S0R = `0' at the time the write operation to S0BG is performed, the timer will not be reloaded until the first instruction cycle after S0R = `1'. For a clean baud rate initialization, S0BG should only be written if S0R = `0'. If S0BG is written with S0R = `1', an unpredicted behavior of the ASC0 may occur during the running of transmit or receive operations. 7.3.3.1 Baud Rates in Asynchronous Mode For asynchronous operation, the baud rate generator provides a clock fBRT with 16 times the rate of the established baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock. The clock divider circuitry, which generates the input clock for the 13-bit baud rate timer, is extended by a fractional divider circuitry, which allows the adjustment of more accurate baud rates and the extension of the baud rate range. The baud rate of the baud rate generator depends on the following bits and register values: * * * * CPU clock Selection of the baud rate timer input clock fDIV by bits S0FDE and S0BRS If bit S0FDE = 1 (fractional divider): value of register S0FDV Value of the 13-bit reload register S0BG The output clock of the baud rate timer with the reload register is the sample clock in the asynchronous modes of the ASC0. For baud rate calculations, this baud rate clock fBR is derived from the sample clock fDIV by a division of 16. Users Manual 7 - 60 2000-06-15 SDA 6000 Peripherals S0FDE Fractional Divider 33 MHz /2 /3 MUX 13-Bit Reload Register / 16 fBR Baud Rate Clock Sample Clock fDIV 13-Bit Baud Rate Timer fBRT S0R S0FDE S0BRS 0 0 1 S0BRS 0 1 X Selected Divider /2 /3 Fractional Divider UES11151 Figure 7-32 ASC0 Baud Rate Generator Circuitry in Asynchronous Modes Using the fixed Input Clock Divider The baud rate for asynchronous operation of serial channel ASC0, when using the fixed input clock divider ratios (S0FDE = 0) and the required reload value for a given baud rate, can be determined by the following formulas: S0FDE 0 S0BRS 0 S0BG 0 ... 8191 Formula 33 MHz Baud rate = 32 x (S0BG+1) S0BG = 33 MHz 32 x Baud rate -1 1 33 MHz Baud rate = 48 x (S0BG+1) S0BG = 33 MHz 48 x Baud rate -1 S0BG represents the content of the reload register S0BG, taken as an unsigned 13-bit integer. The maximum baud rate that can be achieved by the asynchronous modes when using the two fixed clock dividers and a CPU clock of 33.33 MHz is 1041.66 KBaud. The table Users Manual 7 - 61 2000-06-15 SDA 6000 Peripherals below lists various commonly used baud rates, together with the required reload values and the deviation errors compared to the intended baud rate. Baud Rate 1041.66 KBaud 694.4 KBaud 19.2 KBaud 9600 Baud 4800 Baud 2400 Baud 1200 Baud 110 Baud S0BRS = `0', fMOD = 33.33 MHz Deviation Error Reload Value - - + 0.4%/- 1.3% + 0.4%/- 0.4% + 0.0%/- 0.4% + 0.0%/- 0.2% + 0.0%/- 0.1% + 0.0%/- 0.0% 0000H - 0035H/0036H 006bH/006CH 00D8H/00D9H 01B1H/01B2H 0363H/0364H 24FCH/24FDH S0BRS = `1', fMOD = 33.33 MHz Deviation Error Reload Value - - + 0.5%/- 2.2% + 0.5%/- 0.9% + 0.5%/- 0.2% + 0.1%/- 0.2% + 0.1%/- 0.0% + 0.0%/- 0.0% - 0000H 0023H/0024H 0047H/0048H 008FH/0090H 0120H/0121H 0241H/0242H 18A8H/18A9H Note: S0FDE must be equal to 0 to achieve the baud rates in the table above. The deviation errors given in the table are rounded. Using a baud rate crystal will provide correct baud rates without deviation errors. Using the Fractional Divider When the fractional divider is selected, the input clock fDIV for the baud rate timer is derived from the CPU clock by a programmable divider. If S0FDE = 1, the fractional divider is activated, It divides 33.33 MHz by a fraction of n/512 for any value of n from 0 to 511. If n = 0, the divider ratio is 1 which means that fDIV = 33.33 MHz. S0FDE 1 S0BRS - S0BG S0FDV Formula Baud rate = 33MHz S0FDV x 16 x (S0BG+1) 512 1 ... 8191 1 ... 511 0 33MHz Baud rate = 16 x (S0BG+1) S0BG represents the content of the reload register S0BG, taken as an unsigned 13-bit integer. S0FDV represents the content of the fractional divider register taken as an unsigned 9-bit integer. Users Manual 7 - 62 2000-06-15 SDA 6000 Peripherals 7.3.3.2 Baud Rates in Synchronous Mode For synchronous operation, the baud rate generator provides a clock with 4 times the rate of the established baud rate (see Figure 7-33). 13-Bit Reload Register /2 33 MHz /3 S0R S0BRS MUX fDIV 13-Bit Baud Rate Timer fBRT /4 fBR Shift/ Sample Clock S0BRS 0 1 Selected Divider /2 /3 UES11152 Figure 7-33 ASC0 Baud Rate Generator Circuitry in Synchronous Mode The baud rate for synchronous operation of serial channel ASC0 can be determined by the formulas as shown in the following table. S0BRS 0 S0BG 0 ... 8191 Formula 33 MHz Baud rate = 8 x (S0BG+1) 33 MHz Baud rate = 12 x (S0BG+1) S0BG = 33 MHz 8 x Baud rate -1 1 S0BG = 33MHz 12 x Baud rate -1 S0BG represents the content of the reload register, taken as unsigned 13-bit integers. The maximum baud rate that can be achieved in synchronous mode when using a CPU clock of 33.33 MHz is 4.166 MBaud. 7.3.4 Autobaud Detection The autobaud detection unit provides an ability to recognize the mode and the baud rate of an asynchronous input signal at RXD. Generally, the baud rates to be recognized should be known by the application. With this knowledge, a set of nine baud rates can always be detected. The autobaud detection unit is not designed to calculate a baud rate of an unknown asynchronous frame. Users Manual 7 - 63 2000-06-15 SDA 6000 Peripherals Figure 7-34 shows how the autobaud detection unit of the ASC is integrated into its asynchronous mode configuration. The RXD data line is an input of the autobaud detection unit. The clock fDIV, which is generated by the fractional divider, is used by the autobaud detection unit as a time base. After successful recognition of the baud rate and asynchronous operating mode of the RXD data input signal, bits in the CON register and the value of the BG register in the baud rate timer are set to the appropriate values, and the ASC_P3 can start immediately with the reception of serial input data. Asynchronous Mode fMOD Prescaler/ Fractional Divider fDIV Baud Rate Timer Autobaud Detection Serial Port Control RxD MUX IrDA Decoding Receive/Transmit Buffers and Shift Registers MUX IrDA Coding TxD UEB11153 Figure 7-34 ASC_P3 Asynchronous Mode Block Diagram The following sequence must be generally executed to start the operation of the autobaud detection unit: Definition of the baud rates to be detected: standard or non-standard baud rates Programming of the Prescaler/Fractional Divider to select a specific value of fDIV Starting the Prescaler/Fractional Divider (setting CON_R) Preparing the interrupt system of the CPU Enabling the autobaud detection (setting ABCON_ EN and the interrupt enable bits in ABCON for interrupt generation, if required) * Polling interrupt request flag or waiting for the autobaud detection interrupt * * * * * 7.3.4.1 Serial Frames for Autobaud Detection The autobaud detection of the ASC_P3 is based on the serial reception of a specific two-byte serial frame. This serial frame is build up by the two ASCII bytes `at' or `AT' (`aT' or `At' are not allowed). Both byte combinations can be detected in five types of asynchronous frames. Figure 7-35 and Figure 7-36 show the serial frames which are least detected. Users Manual 7 - 64 2000-06-15 SDA 6000 Peripherals Note: Some other two-byte combinations will also be defined. 7 Bit, Even Parity 'a' = 61H 1 Start 0 0 0 0 1 1 1 1 Start 0 0 1 't' = 74 H 0 1 1 1 0 1 Parity Stop Parity Stop 7 Bit, Odd Parity 'a' = 61H 1 Start 0 0 0 0 1 1 0 1 Start 0 0 1 't' = 74 H 0 1 1 1 1 1 Parity Stop Parity Stop 8 Bit, No Parity 'a' = 61H 1 Start 0 0 0 0 1 1 0 1 Stop Start 0 0 1 't' = 74 H 0 1 1 1 0 1 Stop 8 Bit, Even Parity 'a' = 61H 1 Start 0 0 0 0 1 1 0 1 1 Start 0 0 1 't' = 74 H 0 1 1 1 0 0 1 Parity Stop Parity Stop 8 Bit, Odd Parity 'a' = 61H 1 Start 0 0 0 0 1 1 0 0 1 Start 0 0 1 't' = 74 H 0 1 1 1 0 1 1 Parity Stop Parity Stop UED11154 Figure 7-35 Two-Byte Serial Frames with ASCII `at' Users Manual 7 - 65 2000-06-15 SDA 6000 Peripherals 7 Bit, Even Parity 'A' = 41H 1 Start 0 0 0 0 0 1 0 1 Start 0 0 1 'T' = 54 H 0 1 0 1 1 1 Parity Stop Parity Stop 7 Bit, Odd Parity 'A' = 41 H 1 Start 0 0 0 0 0 1 1 1 Start 0 0 1 'T' = 54 H 0 1 0 1 0 1 Parity Stop Parity Stop 8 Bit, No Parity 'A' = 41 H 1 Start 0 0 0 0 0 1 0 1 Stop Start 0 0 1 'T' = 54 H 0 1 0 1 0 1 Stop 8 Bit, Even Parity 'A' = 41 H 1 Start 0 0 0 0 0 1 0 0 1 Start 0 0 1 'T' = 54 H 0 1 0 1 0 1 1 Parity Stop Parity Stop 8 Bit, Odd Parity 'A' = 41 H 1 Start 0 0 0 0 0 1 0 1 1 Start 0 0 1 'T' = 54 H 0 1 0 1 0 0 1 Parity Stop Parity Stop UED11155 Figure 7-36 Two-Byte Serial Frames with ASCII `AT' Users Manual 7 - 66 2000-06-15 SDA 6000 Peripherals 7.3.4.2 Baud Rate Selection and Calculation The autobaud detection requires some calculations concerning the programming of the baud rate generator and the baud rates to be detected. Two steps must be considered: * Defining the baud rate(s) to be detected * Programming of the baud rate timer prescaler - setup of the clock rate of fDIV In general, the baud rate generator of the ASC in asynchronous mode is built up of two parts: * the clock prescaler part which derives fDIV from fMOD * the baud rate timer part which generates the sample clock fBRT and the baud rate clock fBR Prior to an autobaud detection, the prescaler part has to be set up by the CPU while the baud rate timer (register BG) is automatically initialized with a 13-bit value (BR_VALUE) after a successfull autobaud detection. For the subsequent calculations, the fractional divider is used (CON_FDE = 1). Note: It is also possible to use the fixed divide-by-2 or divide-by-3 prescaler. But the fractional divider allows for a more precise adaption of fDIV to the required value. Standard Baud Rates For standard baud rate detection the baud rates as shown in Table 7-20 can be detected. Therefore, the output frequency fDIV of the ASC baud rate generator must be set to a frequency derived from the system, clocked (33 MHz) in a way that it is equal to 11.0592 MHz. The value to be written into register FDV is the nearest integer value which is calculated according the following formula: 512 x 11.0592 MHz 33 MHz FDV = Table 7-20 defines the nine standard baud rates (Br0 - Br8) which can be detected for fDIV = 11.0592 MHz. Users Manual 7 - 67 2000-06-15 SDA 6000 Peripherals Table 7-20 Baud Rate Numbering Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 Autobaud Detection using Standard Baud Rates (fDIV = 11.0592 MHz) Detectable Standard Baud Rate 230.400 kBaud 115.200 kBaud 57.600 kBaud 38.400 kBaud 19.200 kBaud 9600 Baud 4800 Baud 2400 Baud 1200 Baud Divide Factor df 48 96 192 288 576 1152 2304 4608 9216 BG is Loaded after Detection with Value 2 5 = 002H = 005H 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH According to Table 7-20 a baud rate of 9600 Baud is achieved when register BG is loaded with a value of 047H, assuming that fDIV has been set to 11.0592 MHz. Table 7-20 also lists a divide factor d f which is defined with the following formula: baud rate = f DIV df This divide factor df defines a fixed relationship between the prescaler output frequency fDIV and the baud rate to be detected during the autobaud detection operation. This means, that changing fDIV results in a totally different baud rate table in terms of baud rate values. For the baud rates to be detected, the following relations are always valid: - Br0 = fDIV/48D, Br1 = fDIV/96D, ... up to Br8 = fDIV/9216D, A requirement for detecting standard baud rates up to 230.400 kBaud, is the fDIV minimum value of 11.0592 MHz. With the value FD_VALUE in register FDV, the fractional divider fDIV is adapted to the system clock frequency 33 MHz. Table 7-21 defines the deviation of the standard baud rates when using autobaud detection depending on the system fMOD. Table 7-21 Standard Baud Rates - Deviations and Errors for Autobaud Detection FDV 172 Error in fDIV + 0.24% fMOD 33 MHz Users Manual 7 - 68 2000-06-15 SDA 6000 Peripherals Note: If the deviation of the baud rate after autobaud detection is too high, the baud rate generator (fractional divider FDV and reload register BG) can be reprogrammed if required to get a more precise baud rate with less error. Non-Standard Baud Rates Due to the relationship between Br0 to Br8 in Table 7-20 concerning the divide factor df other baud rates than the standard ones can also be selected. For example, if a baud rate of 50 kBaud has to be detected, Br2 is e.g. defined as baud rate for the 50 kBaud detection. This further results in: - fDIV = 50 kBaud x df@Br2 = 50 kBaud x 192 = 9.6 MHz Therefore, depending on the system clock frequency, the value of the fractional divider (register FDV must be set according the formula in this example: FDV = 512 x fDIV 33 MHz with fDIV = 9.6 MHz Using this selection (fDIV = 9.6 MHz), the detectable baud rates start at 200 kBaud (Br0) down to 1042 Baud (Br8). Table 7-22 shows the baud rate table for this example. Table 7-22 Baud Rate Numbering Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 Autobaud Detection using Non-Standard Baud Rates (fDIV = 9.6 MHz) Detectable Non-Standard Baud Rates 200.000 kBaud 100.000 kBaud 50 kBaud 33.333 kBaud 16.667 kBaud 8333 Baud 4167 Baud 2083 Baud 1047 Baud Divide Factor df BG is Loaded after Detection with Value 2 5 = 002H = 005H 48 96 192 288 576 1152 2304 4608 9216 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH 7.3.4.3 Overwriting Registers on Successful Autobaud Detection With a successful autobaud detection, some bits in register CON and BG are automatically set to a value which corresponds to the mode and baud rate of the detected serial frame conditions. In control register CON the mode control bits CON_M Users Manual 7 - 69 2000-06-15 SDA 6000 Peripherals and the parity select bit CON_ODD are overwritten. Register BG is loaded with the 13-bit reload value for the baud rate timer. Table 7-23 Autobaud Detection Overwrite Values for the CON Register CON_M 011 011 111 111 001 - CON_ODD BG_BR_VALUE 0 1 0 1 0 - - 7 bit, even parity 7 bit, odd parity 8 bit, even parity 8 bit, odd parity 8 bit, no parity Br0 Br1 Br2 Br3 Br4 Br5 Br6 Br7 Br8 Detected Parameters Operating Mode Baud rate 2 = 002H 5 = 005H 11 = 00BH 17 = 011H 35 = 023H 71 = 047H 143 = 08FH 287 = 11FH 575 = 23FH 7.3.5 ASC Hardware Error Detection Capabilities To improve the safety of serial data exchange, the serial channel ASC0 provides an error interrupt request flag, which indicates the presence of an error, and three (selectable) error status flags in register S0CON, which indicate which error has been detected during reception. Upon completion of a reception, the error interrupt request line S0EIR will be activated simultaneously with the receive interrupt request line S0RIR if one or more of the following conditions are met: * The framing error detection enable bit S0FEN is set and any of the expected stop bits are not high, the framing error flag S0FE is set, indicating that the error interrupt request is due to a framing error (Asynchronous mode only). * If the parity error detection enable bit S0PEN is set in the mode where a parity bit is received, and the parity check on the received data bits proves false, the parity error flag S0PE is set, indicating that the error interrupt request is due to a parity error (Asynchronous mode only). * If the overrun error detection enable bit S0OEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete, the overrun error flag S0OE is set, indicating that the error interrupt request is due to an overrun error (Asynchronous and synchronous mode). Users Manual 7 - 70 2000-06-15 SDA 6000 Peripherals 7.3.6 Interrupts Six interrupt sources are provided for serial channel ASC0. Line S0TIC indicates a transmit interrupt, S0TBIC indicates a transmit buffer interrupt, S0RIC indicates a receive interrupt and S0EIC indicates an error interrupt of the serial channel. The autobaud detection unit provides two additional interrupts, the ABSTIR start of autobaud operation interrupt and the ABDETIR autobaud detected interrupt. The interrupt output lines S0TBIR, S0TIR, S0RIR, and S0EIR are activated (active state) for two periods of the module clock fMOD (33.33 MHz). The cause of an error interrupt request (framing, parity, overrun error) can be identified by the error status flags S0FE, S0PE, and S0OE which are located in control register S0CON. Note: In contrary to the error interrupt request line S0EIR, the error status flags S0FE/ S0PE/S0OE are not reset automatically but must be cleared by software. For normal operation (e.g. besides the error interrupt) the ASC0 provides three interrupt requests to control data exchange via this serial channel: * S0TBIR is activated when data is moved from S0TBUF to the transmit shift register. * S0TIR is activated before the last bit of an asynchronous frame is transmitted, or after the last bit of a synchronous frame has been transmitted. * S0RIR is activated when the received frame is moved to S0RBUF. While the task of the receive interrupt handler is quite clear, the transmitter is serviced by two interrupt handlers. This has its advantages for the servicing software. For single transfers it is sufficient to use the transmitter interrupt (S0TIR), which indicates that the previously loaded data, except for the last bit of an asynchronous frame, has been transmitted. For multiple back-to-back transfers it is necessary to wait to load the last piece of data until the last bit of the previous frame has been transmitted. In asynchronous mode this leaves just one bit-time for the handler to respond to the transmitter interrupt request, in synchronous mode it is impossible. Using the transmit buffer interrupt (S0TBIR) to reload transmitted data gives enough time to transmit a complete frame for the service routine, as S0TBUF may be reloaded while the previous data is still being transmitted. The ABSTIR start of autobaud operation interrupt is generated whenever the autobaud detection unit is enabled (ABEN, ABDETEN and ABSTEN set), and a start bit has been detected at RXD. In this case ABSTIR is generated during autobaud detection whenever a start bit is detected. The ABDETIR autobaud detected interrupt is always generated after recognition of the second character of the two-byte frame, after a successful autobaud detection. If ABCON_FCDETEN is set the ABDETIR autobaud detected interrupt is also generated after the recognition of the first character of the two-byte frame. Users Manual 7 - 71 2000-06-15 SDA 6000 Peripherals Asynchronous Mode S0TBIR S0TIR S0TBIR S0TIR S0TBIR S0TIR Start Start Start Stop Stop Idle Stop 4 3 2 1 Idle S0RIR S0RIR S0RIR Synchronous Mode S0TBIR S0TIR S0TBIR S0TIR S0TBIR S0TIR Idle Idle S0RIR S0RIR S0RIR UED11156 Figure 7-37 ASC0 Interrupt Generation As shown in Figure 7-37, S0TBIR is an early trigger for the reload routine, while S0TIR indicates the completed transmission. Software using handshake therefore should rely on S0TIR at the end of a data block to make sure that all data has really been transmitted. 7.3.7 Register Description The operating mode of the serial channel ASC0 is controlled by its control register S0CON. This register contains control bits for mode and error check selection, and status flags for error identification. S0CON Control Register 15 14 13 12 11 10 9 8 7 6 5 0 R LB BRS ODD FDE OE FE PE OEN FEN PEN / REN RXD I STP M Users Manual 7 - 72 2000-06-15 SDA 6000 Peripherals Field M Bits 2-0 Type rwh Value 000 001 010 011 100 101 110 111 Description Mode Selection 8-bit data sync. operation 8-bit data async. operation IrDA mode, 8-bit data async. operation 7-bit data + parity async. operation 9-bit data async. operation 8-bit data + wake up bit async. operation Reserved. Do not use this combination! 8-bit data + parity async. operation Bits are set/cleared by hardware after a successful autobaud detection operation. Number of Stop Bit Selection One stop bit Two stop bits Receiver Enable Control Receiver disabled Receiver enabled Bit can be affected during autobaud detection operation when bit ABEN_AUREN is set. Bit is reset by hardware after reception of byte in synchronous mode. Parity Check Enable/ IrDA Input Inverter Enable All asynchronous modes without IrDA mode: Ignore parity Check parity Only in IrDA mode (M = 010): RXD input is not inverted RXD input is inverted Framing Check Enable (async. modes only) Ignore framing errors Check framing errors Overrun Check Enable Ignore overrun errors Check overrun errors STP 3 rw 0 1 REN 4 rwh 0 1 PEN RXDI 5 rw 0 1 0 1 FEN 6 rw 0 1 OEN 7 rw 0 1 Users Manual 7 - 73 2000-06-15 SDA 6000 Peripherals Field PE Bits 8 Type rwh Value - Description Parity Error Flag Set by hardware on a parity error (PEN = `1'). Must be reset by software. Framing Error Flag Set by hardware on a framing error (FEN = `1'). Must be reset by software. Overrun Error Flag Set by hardware on an overrun error (OEN = `1'). Must be reset by software. Fractional Divider Enable Fractional divider disabled Fractional divider is enabled and used as prescaler for baud rate timer (bit BRS is don't care). Parity Selection Even parity selected (parity bit set on odd number of `1's in data) Odd parity selected (parity bit set on even number of `1's in data) Bit is be set/cleared by hardware after a successful autobaud detection operation. Baud rate Selection Baud rate timer prescaler divide-by-2 selected Baud rate timer prescaler divide-by-3 selected BRS is don't care if FDE = 1 (fractional divider enabled) Loop-back Mode Enable Loop-back mode disabled Loop-back mode enabled Baud rate Generator Run Control Baud rate generator disabled (ASC_P inactive) Baud rate generator enabled BG should only be written if R = `0'. FE 9 rwh - OE 10 rwh - FDE 11 rw 0 1 ODD 12 rwh 0 1 BRS 13 rw 0 1 LB 14 rw 0 1 R 15 rw 0 1 Users Manual 7 - 74 2000-06-15 SDA 6000 Peripherals The autobaud control register ABCON is used to control the autobaud detection operation. It contains its general enable bit, the interrupt enable control bits, and data path control bits . S0ABCON Autobaud Control Register 15 0 14 0 13 0 12 0 11 RX INV 10 TX INV 9 8 7 0 6 0 5 0 4 FC DET EN 3 AB DET EN 2 1 0 AB EN ABEM ABS AUR T EN EN Field ABEN Bits 0 Type rwh Value Description 0 1 Autobaud Detection Enable Autobaud detection is disabled Autobaud detection is enabled ABEN is reset by hardware after a successful autobaud detection; (with the stop bit detection of the second character). Resetting ABEN by software if it was set aborts the autobaud detection. Automatic Autobaud Control of CON_REN CON_REN is not affected during autobaud detection CON_REN is cleared (receiver disabled) when ABEN and AUREN are set together. CON_REN is set (receiver enabled) after a successful autobaud detection (with the stop bit detection of the second character). Start of Autobaud Detection Interrupt Enable Start of autobaud detection interrupt disabled Start of autobaud detection interrupt enabled Autobaud Detection Interrupt Enable Autobaud detection interrupt disabled Autobaud detection interrupt enabled AUREN 1 rw 0 1 ABSTEN 2 rw 0 1 ABDETEN 3 rw 0 1 Users Manual 7 - 75 2000-06-15 SDA 6000 Peripherals Field FCDETEN Bits 4 Type rw 0 Value Description First Character of Two-Byte Frame Detected Enable Autobaud detection interrupt ABDETIR becomes active after the two-byte frame recognition Autobaud detection interrupt ABDETIR becomes active after detection of the first and second byte of the two-byte frame. Autobaud Echo Mode Enable In echo mode the serial data at RXD is switched to TXD output. Echo mode disabled Echo mode is enabled during autobaud detection Echo mode is always enabled reserved Transmit Inverter Enable Transmit inverter disabled Transmit inverter enabled Receive Inverter Enable Receive inverter disabled Receive inverter enabled 1 ABEM 8-9 rw 00 01 10 11 TXINV 10 rw 0 1 RXINV 11 rw 0 1 The autobaud status register ABSTAT indicates the status of the autobaud detection operation. Users Manual 7 - 76 2000-06-15 SDA 6000 Peripherals S0ABSTAT Autobaud Status Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 DET WAI T 3 SCC DET 2 SCS DET 1 FCC DET 0 FCS DET Field FCSDET Bits 0 Type rwh Value Description First Character with Small Letter Detected no small `a' character detected small `a' character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCCDET or SCSDET or SCCDET is set. Bit can be also cleared by software. First Character with Capital Letter Detected no capital `A' character detected capital `A' character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCSDET or SCSDET or SCCDET is set. Bit can be also cleared by software. Second Character with Small Letter Detected no small `t' character detected small `t' character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCSDET or FCCDET or SCCDET is set. Bit can be also cleared by software. 0 1 FCCDET 1 rwh 0 1 SCSDET 2 rwh 0 1 Users Manual 7 - 77 2000-06-15 SDA 6000 Peripherals Field SCCDET Bits 3 Type rwh Value Description Second Character with Capital Letter Detected no capital `T' character detected capital `T' character detected Bit is cleared by hardware when ABCON_ABEN is set or if FCSDET or FCCDET or SCSDET is set. Bit can be also cleared by software. Autobaud Detection is Waiting Either character `a', `A', `t', or `T' has been detected. The autobaud detection unit waits for the first `a' or `A' Bit is cleared when either FCSDET or FCCDET is set (`a' or `A' detected). Bit can be also cleared by software. DETWAIT is set by hardware when ABCON_ABEN is set. 0 1 DETWAIT 4 rwh 0 1 Note: SCSDET or SCCDET are set when the second character has been recognized. CON_ABEN is reset, and ABDETIR set, after SCSDET or SCCDET have seen set. The baud rate timer reload register BG contains the 13-bit reload value for the baud rate timer in asynchronous and sychronous mode. Users Manual 7 - 78 2000-06-15 SDA 6000 Peripherals S0BG Baud Rate Timer/Reload Register 15 0 14 0 13 0 12 11 10 9 8 7 6 BR_VALUE 5 4 3 2 1 0 Field BR_VALUE Bits 12-0 Type Value Description rw all Baud Rate Timer/Reload Register Value Reading BG returns the 13-bit content of the baud rate timer (bits 15 ... 13 return 0); writing BG loads the baud rate timer reload register (bits 15 ... 13 are don't care). BG should only be written if CON_R = `0'. The fractional divider register FDV contains the 9-bit divider value for the fractional divider (asynchronous mode only). It is also used for reference clock generation of the autobaud detection unit. S0FDV Fractional Divider Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 FD_VALUE 3 2 1 0 Field FD_VALUE Bits 8-0 Type rw Value Description all Fractional Divider Register Value FDV contains the 9-bit value n of the fractional divider which defines the fractional divider ratio: n/512 n = 0-511). With n = 0, the fractional divider is switched off (input = output frequency, fDIV = fMOD). The IrDA pulse mode and width register PMW contains the 8-bit IrDA pulse width value and the IrDA pulse width mode select bit. This register is only required in the IrDA operating mode. Users Manual 7 - 79 2000-06-15 SDA 6000 Peripherals S0PMW IrDA Pulse Mode/Width Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 IRP W 7 6 5 4 3 2 1 0 PW_VALUE Field PW_VALUE Bits 7-0 Type Value Description rw all IrDA Pulse Width Value PW_VALUE is the 8-bit value n, which defines the variable pulse width of an IrDA pulse. Depending on the ASC_P input frequency fMOD, this value can be used to adjust the IrDA pulse width to value which is not equal 3/16 bit time (e.g. 1.6 s). IrDA Pulse Width Mode Control IrDA pulse width is 3/16 of the bit time IrDA pulse width is defined by PW_VALUE IRPW 8 rw 0 1 The transmitter buffer register TBUF contains the transmit data value in asynchronous and synchronous modes. Users Manual 7 - 80 2000-06-15 SDA 6000 Peripherals S0TBUF Transmitter Buffer Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 TD_VALUE 3 2 1 0 Field TD_VALUE Bits 8-0 Type rw Value Description all Transmit Data Register Value TBUF contains the data to be transmitted in asynchronous and synchronous operating mode of the ASC_P. Data transmission is double buffered, therefore, a new value can be written to TBUF before the transmission of the previous value is complete. The receiver buffer register RBUF contains the receive data value in asynchronous and synchronous modes. S0RBUF Transmitter Buffer Register 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 RD_VALUE 3 2 1 0 Field RD_VALUE Bits 8-0 Type rw Value Description all Receive Data Register Value RBUF contains the received data bits and, depending on the selected mode, the parity bit in asynchronous and synchronous operating mode of the ASC_P. In asynchronous operating mode with M = 011 (7-bit data + parity), the received parity bit is written into RD7. In asynchronous operating mode with M = 111 (8-bit data + parity) the received parity bit is written into RD8. Users Manual 7 - 81 2000-06-15 SDA 6000 Peripherals 7.4 High Speed Synchronous Serial Interface * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits: 2 to 16 bit - Programmable shift direction: LSB or MSB shift first - Programmable clock polarity: idle low or high state for the shift clock - Programmable clock/data phase: data shift with leading or trailing edge of SCLK * Baud rate generation from 12.5 MBaud to 190.7 Baud (@ 25 MHz module clock) * Interrupt generation - on a transmitter empty condition - on a receiver full condition - on an error condition (receive, phase, baud rate, transmit error) * Three pin interface - Flexible SSC0 pin configuration The High Speed Synchronous Serial Interface SSC0 provides serial communication between M2 and other microcontrollers, microprocessors or external peripherals. It is compatible with the SSC0 of the referred C161RI device with the following extensions: * Maximum SSC clock in master mode: fSCLK max. 16.5 MHz. Maximum SSC clock in slave mode: fSCLK max. 8.25 MHz. * Reload value 0000H is allowed in master mode. * Because of the symmetric SSC clock requirement in master mode (50% duty cycle), the divide-by-2 prescaler is required. * The counter of the baud rate generator is only active (running) during a transmit or receive operation. * The transmit interrupt becomes active when a transmission starts. The SSC0 registers can be basically divided into three types of registers as shown in Figure 7-38. Users Manual 7 - 82 2000-06-15 SDA 6000 Peripherals Ports & Direction Control Alternate Functions ODP3 DP3 P3 SLCK/P3.13 MTSR/P3.9 MRST/P3.8 ODP3 DP3 SSCBR SSCTB SSCTIC Data Registers Control Registers Interrupt Control SSCBR SSCTB SSCRB SSCCON SSCTIC SSCRIC SSCEIC Port 3 Open Drain Control Register Port 3 Direction Control Register SSC Baud Rate Generator/Reload Register SSC Transmit Buffer Register (write only) SSC Transmit Interrupt Control Register P3 SSCCON SSCRB SSCRIC SSCEIC Port 3 Data Register SSC Control Register SSC Receive Buffer Register (read only) SSC Receive Interrupt Control Register SSC Error Interrupt Control Register UEA11157 Figure 7-38 SFRs and Port Pins Associated with the SSC0 The SSC0 supports full-duplex and half-duplex synchronous communication up to 16.5 MBaud (@ 33.33 MHz module clock). The serial clock signal can be generated by the SSC0 itself (master mode), or received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. The high-speed synchronous serial interface can be configured in a very flexible way, so it can be used with other synchronous serial interfaces, serve for master/slave or multimaster interconnections or operate compatible with the popular SPI interface. So it can be used to communicate with shift registers (I/O expansion), peripherals (e.g. EEPROMs etc.) or other controllers (networking). The SSC0 supports half-duplex and full-duplex communication. Data is transmitted or received on pins MTSR0 (Master Transmit/Slave Receive) and MRST0 (Master Receive/Slave Transmit). The clock signal is output or input on pin SCLK0. These pins are alternate functions of port pins. Users Manual 7 - 83 2000-06-15 SDA 6000 Peripherals 33 MHz Baud Rate Generator Clock Control Shift Clock SSC Control Block SSC0CON SSC0RIR SSC0TIR SSC0EIR SCLKx Receive Int. Request Transmit Int. Request Error Int. Request Status Control MTSRx Pin Control 16-Bit Shift Register MRSTx Transmit Buffer Register SSC0TB Internal Bus Receive Buffer Register SSC0RB UEB11158 Figure 7-39 Synchronous Serial Channel SSC0 Block Diagram The operating mode of the serial channel SSC0 is controlled by its bit-addressable control register SSCC0N. This register serves two purposes: * during programming (SSC0 disabled by SSC0EN = `0') it provides access to a set of control bits * during operation (SSC enabled by SSC0EN = `1') it provides access to a set of status flags The shift register of the SSC0 is connected to both the transmit pin and the receive pin via the pin control logic (see block diagram in Figure 7-39). Transmission and reception of serial data is synchronized and takes place at the same time, e.g. the same number of transmitted bits is also received. Transmit data is written into the Transmit Buffer SSCTB. It is moved to the shift register as soon as this is empty. An SSC master (SSC0MS = `1') immediately begins transmitting, while an SSC slave (SSC0MS = `0') will wait for an active shift clock. When the transfer starts, the busy flag SSC0BSY is set and a transmit interrupt request line (SSCTIR) will be activated to indicate that SSCTB may be reloaded again. When the programmed number of bits (2 ... 16) has been Users Manual 7 - 84 2000-06-15 SDA 6000 Peripherals transferred, the contents of the shift register are moved to the Receive Buffer SSCRB and a receive interrupt request line (SSCRIR) will be activated. If no further transfer is to take place (SSCTB is empty), SSC0BSY will be cleared at the same time. Software should not modify SSC0BSY, as this flag is hardware controlled. Note: Only one SSC (etc.) can be master at a given time. The transfer of serial data bits can be programmed in many respects: * * * * * The data width can be chosen from 2 bits to 16 bits A transfer may start with the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading or trailing edge of the clock signal The baud rate may be set from 254 Baud up to 16.66 MBaud (@ 33.33 MHz module clock) * The shift clock can be generated (master) or received (slave) These features allow the adaptation of the SSC0 to a wide range of applications, where serial data transfer is required. The Data Width Selection supports the transfer of frames of any data length, from 2-bit `characters' up to 16-bit `characters'. Starting with the LSB (SSC0HB = `0') allows communication e.g. with an SSC device in synchronous mode (C166 family) or 8051 like serial interfaces. Starting with the MSB (SSC0HB = `1') allows operation compatible with the SPI interface. Regardless which data width is selected and whether the MSB or the LSB is transmitted first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the LSB of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the internal shift register logic. The unselected bits of SSCTB are ignored, the unselected bits of SSCRB will not be valid and should be ignored by the receiver service routine. The Clock Control allows the transmit and receive behavior of the SSC0 to be adapted to a variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit data, while the other clock edge is used to latch in receive data. Bit SSC0PH selects the leading edge or the trailing edge for each function. Bit SSC0PO selects the level of the clock line in the idle state. So for an idle-high clock the leading edge is a falling one, a 1-to-0 transition (see Figure 7-40). Users Manual 7 - 85 2000-06-15 SDA 6000 Peripherals SSC0 SSC0 PO PH 0 0 1 1 0 1 0 1 Shift Clock SCLK Pins MTSR0/MRST0 First Bit Latch Data Shift Data Transmit Data Last Bit UED11159 Figure 7-40 Serial Clock Phase and Polarity Options 7.4.1 Full-Duplex Operation The different devices are connected by three lines. The definition of these lines is always determined by the master: the line connected to the master's data output pin MTSR is the transmit line, the receive line is connected to its data input line MRST, and the clock line is connected to pin SCLK. Only the device selected for master operation generates and outputs the serial clock on pin SCLK. All slaves receive this clock, so their pin SCLK must be switched to input mode. The output of the master's shift register is connected to the external transmit line, which in turn is connected to the slaves' shift register input. The output of the slaves' shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave. The external connections are hard-wired, the function and direction of these pins is determined by the master or slave operation of the individual device. Note: The shift direction shown in the diagram applies to MSB-first operation as well as to LSB-first operation. When initializing the devices in this configuration, one device must be selected for master operation while all other devices must be programmed for slave operation. Initialization includes the operating mode of the device's SSC and also the function of the respective port lines. Users Manual 7 - 86 2000-06-15 SDA 6000 Peripherals Device #1 Shift Register Master MTSR Device #2 Shift Register Transmit MTSR Slave MRST Receive MRST Clock CLK Clock CLK Clock Device #3 Shift Register MTSR Slave MRST CLK Clock UED11160 Figure 7-41 SSC0 Full Duplex Configuration The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration. During a transfer; each slave shifts out data from its shift register. There are two ways to avoid collisions on the receive line due to different slave data: * Only one slave drives the line, e.g. enables the driver of its MRST pin. All the other slaves have to program their MRST pins to input. So only one slave can put its data onto the master's receive line. Only receiving of data from the master is possible. The master selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. The selected slave then switches its MRST line to output, until it gets a deselection signal or command. * The slaves use open drain output on MRST. This forms a wired-AND connection. The receive line needs an external pullup in this case. Corruption of the data on the receive line sent by the selected slave is avoided, when all slaves which are not selected for transmission to the master only send ones (`1'). Since this high level is not actively driven onto the line, but only held through the pullup device, the selected slave can actively pull this line to a low level when transmitting a zero bit. The master Users Manual 7 - 87 2000-06-15 SDA 6000 Peripherals selects the slave device from which it expects data either by separate select lines, or by sending a special command to this slave. After performing all necessary initializations of the SSC0, the serial interfaces can be enabled. In a master device, the alternate clock line will now go to its programmed polarity. The alternate data line will go to either `0' or `1', until the first transfer starts. After a transfer, the alternate data line will always remain at the logic level of the last transmitted data bit. When the serial interfaces are enabled, the master device can initiate the first data transfer by writing the transmit data into register SSCTB. This value is copied into the shift register (which is assumed to be empty at this time), and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock to the baud rate generator (transmission only starts, if SSC0EN = `1'). Depending on the selected clock phase, a clock pulse will also be generated on the SCLK line. With the opposite clock edge the master simultaneously latches and shifts in the data detected at its input line MRST. This `exchanges' the transmit data with the receive data. Since the clock line is connected to all slaves, their shift registers will be shifted synchronously with the master's shift register, shifting out the data contained in the registers, and shifting in the data detected at the input line. After the pre-programmed number of clock pulses (via the data width selection) the data transmitted by the master is contained in all slaves' shift registers, while the master's shift register holds the data of the selected slave. In the master and all the slaves, the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt line SSC0RIR is activated. A slave device will immediately output the selected first bit (MSB or LSB of the transfer data) at pin MRST, when the content of the transmit buffer is copied into the slave's shift register. It will not wait for the next clock from the baud rate generator, as the master does. The reason for this is that, depending on the selected clock phase, the first clock edge generated by the master may be already used to clock in the first data bit. So the slave's first data bit must already be valid at this time. Note: On the SSC0 a transmission and a reception always takes place at the same time, regardless whether valid data has been transmitted or received. The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions, which may disturb the other receivers. The state of the internal alternate output lines is `1' as long as the SSC is disabled. This alternate output signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-low clock (SSC0PO = `0') will immediately drive the alternate data output and (via the AND) the port pin SCLK low. To avoid this, the following sequence should be used: * * * * * select the clock idle level (SSC0PO = `x') load the port output latch with the desired clock idle level switch the pin to output enable the SSC0 (SSC0EN = `1') if SSC0PO = `0': enable alternate data output 7 - 88 2000-06-15 Users Manual SDA 6000 Peripherals The same mechanism as for selecting a slave for transmission (separate select lines or special commands) may also be used to move the role of the master to another device in the network. In this case the previous master and the future master (previous slave) will have to toggle their operating mode (SSC0MS) and the direction of their port pins. 7.4.2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data. The data exchange line is connected to both the MTSR and MRST pins in each device, the clock line is connected to the SCLK pin. The master device controls the data transfer by generating the shift clock, while the slave devices receive it. Due to the fact that all transmit and receive pins are connected to the one data exchange line, serial data may be moved between arbitrary stations. Similar to full duplex mode there are two ways to avoid collisions on the data exchange line: * only the transmitting device may enable its transmit pin driver * the non-transmitting devices use open drain output and only send ones. Since the data inputs and outputs are connected together, a transmitting device will clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By these means any corruptions on the common data exchange line, where the received data is not equal to the transmitted data are detected. Users Manual 7 - 89 2000-06-15 SDA 6000 Peripherals Device #1 Shift Register Master MTSR Transmit Device #2 Shift Register MTSR Slave MRST MRST Clock CLK Clock CLK Clock Common Transmit/ Receive Line Device #3 Shift Register MTSR Slave MRST CLK Clock UED11161 Figure 7-42 SSC Half Duplex Configuration 7.4.3 Continuous Transfers When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data. If SSCTB has been reloaded by the time the current transmission is finished, the data is immediately transferred to the shift register and the next transmission starts without any additional delay. On the data line there is no gap between the two successive frames. For example, two byte transfers would look the same as one word transfer. This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer. How long a total data frame length can be depends on the software. This option can also be used e.g. to interface to byte-wide and word-wide devices on the same serial bus. Note: Of course, this can only happen in multiples of the selected basic data width, since it would require disabling/enabling of the SSC0 to reprogram the basic data width on-the-fly. Users Manual 7 - 90 2000-06-15 SDA 6000 Peripherals 7.4.4 Port Control The SSC0 uses three pins to communicate with the external world. Pin SCLK serves as the clock line, while pins MRST (Master Receive/Slave Transmit) and MTSR (Master Transmit/Slave Receive) serve as the serial data input/output lines. The operation of the SSC0 pins depends on the selected operating mode (master or slave). The direction of the port lines depends on the operating mode. The SSC0 will automatically use the correct alternate input or output line of the ports when switching modes. The direction of the port pins, however, must be programmed by the user. Using the open drain output feature of the port lines helps to avoid bus contention problems and reduces the need for hardwired hand-shaking or slave select lines. In this case it is not always necessary to switch the direction of a port pin. 7.4.5 Baud Rate Generation The serial channel SSC0 has its own dedicated 16-bit baud rate generator with 16-bit reload capability, allowing baud rate generation independent from the timers. In addition to Figure 7-39, Figure 7-43 shows the baud rate generator of the SSC0 in more detail. 16-Bit Reload Register 33 MHz /2 16-Bit Counter fSCLK fSCLKmax in master mode < 33 MHz / 2 _ fSCLKmax in slave mode < 33 MHz / 4 _ UES11162 Figure 7-43 SSC0 Baud Rate Generator The baud rate generator is clocked with the module clock 33.33 MHz. The timer is counting downwards. Register SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while the SSC0 is enabled, returns the content of the timer. Reading SSCBR, while the SSC0 is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCBR. Note: Never write to SSCBR, while the SSC0 is enabled. Users Manual 7 - 91 2000-06-15 SDA 6000 Peripherals The formulas below calculate either the resulting baud rate for a given reload value, or the required reload value for a given baud rate: Baud rateSSC0 = 33 MHz 2 x ( 33 MHz 2 x Baud rateSSC0 )-1 7.4.6 Error Detection Mechanisms The SSC0 is able to detect four different error conditions. Receive Error and Phase Error are detected in all modes, while Transmit Error and baud rate Error only apply to slave mode. When an error is detected, the respective error flag is set and an error interrupt request will be generated by activating the SSCEIR line (see Figure 7-44). The error interrupt handler may then check the error flags to determine the cause of the error interrupt. The error flags are not reset automatically but rather must be cleared by software after servicing. This allows some error conditions to be serviced via interrupt, while the others may be polled by software. Note: The error interrupt handler must clear the associated (enabled) error-flag(s) to prevent repeated interrupt requests. Users Manual 7 - 92 2000-06-15 SDA 6000 Peripherals Bit in Register SSCCON SSC0TEN & Transmit Error SSC0TE SSC0REN & Receive Error SSC0RE _ <1 Error Interrupt SSCEIR SSC0PEN & Phase Error SSC0PE SSC0BEN & Baud Rate Error SSC0BE UES11163 Figure 7-44 SSC0 Error Interrupt Control A Receive Error (Master or Slave mode) is detected, when a new data frame is completely received, but the previous data was not read out of the receive buffer register SSCRB. This condition sets the error flag SSC0RE and, when enabled via SSC0REN, the error interrupt request line SSCEIR. The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost. A Phase Error (Master or Slave mode) is detected, when the incoming data at pin MRST0 (master mode) or MTSR0 (slave mode), sampled with the same frequency as the module clock, changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK. This condition sets the error flag SSC0PE and, when enabled via SSC0PEN, the error interrupt request flag SSCEIR. A Baud Rate Error (Slave mode) is detected, when the incoming clock signal deviates from the programmed baud rate by more than 100%, e.g. it is either more than double or less than half the expected baud rate. This condition sets the error flag SSC0BE and, when enabled via SSC0BEN, the error interrupt request line SSCEIR. Using this error detection capability requires that the slave's baud rate generator is programmed to the same baud rate as the master device. This feature detects false additional, or missing pulses on the clock line (within a certain frame). Users Manual 7 - 93 2000-06-15 SDA 6000 Peripherals Note: If this error condition occurs and bit SSC0REN = `1', an automatic reset of the SSC0 will be performed in case of this error. This is done to re-initialize the SSC0, if too few or too many clock pulses have been detected. A Transmit Error (Slave mode) is detected, when a transfer is initiated by the master (shift clock gets active), but the transmit buffer SSCTB of the slave was not updated since the last transfer. This condition sets the error flag SSC0TE and, when enabled via SSC0TEN, the error interrupt request line SSC0EIR. If a transfer starts while the transmit buffer is not updated, the slave will shift out the `old' contents of the shift register, which is normally the data received during the last transfer. This may lead to the corruption of the data on the transmit/receive line in half-duplex mode (open drain configuration), if this slave is not selected for transmission. This mode requires that slaves not selected for transmission only shift out ones, e.g. their transmit buffers must be loaded with `FFFFH' prior to any transfer. Note: A slave with push/pull output drivers, which is not selected for transmission, will normally have its output drivers switched. However, in order to avoid possible conflicts or misinterpretations, it is recommended to always load the slave's transmit buffer prior to any transfer. The cause of an error interrupt request (receive, phase, baud rate, transmit error) can be identified by the error status flags in control register SSCCON. Note: In contrary to the error interrupt request line SSCEIR, the error status flags SSC0TE, SSC0RE, SSC0PE, and SSC0BE, which are located in register SSCCON, are not reset automatically upon entry into the error interrupt service routine, but must be cleared by software. Users Manual 7 - 94 2000-06-15 SDA 6000 Peripherals 7.4.7 Register Description The operating mode of the serial channel SSC0 is controlled by its control register SSCCON. This register contains control bits for mode and error check selection, and status flags for error identification. Depending on bit SSC0EN, either control functions or status flags and master/slave control is enabled. SSC0EN = 0: Programming Mode SSCCON 15 14 13 - Reset Value: 0000H 12 11 10 9 8 7 6 5 SSC0 PH 4 SSC0 HB 3 2 1 0 SSC0 SSC0 EN MS SSC0 SSC0 SSC0 AREN BEN PEN SSC0 SSC0 REN TEN SSC0 SSC0 LB PO SSC0BM rw rw rw rw rw rw rw rw rw rw rw rw Bit SSC0BM Function SSC0 Data Width Selection 0: Reserved. Do not use this combination. 1 ... 15: Transfer Data Width is 2 ... 16 bit ( SSC0HB SSC0PH SSC0PO SSC0LB SSC0TEN SSC0REN Users Manual 7 - 95 2000-06-15 SDA 6000 Peripherals Bit SSC0PEN Function SSC0 Phase Error Enable Bit 0: Ignore phase errors 1: Check phase errors SSC0 Baud Rate Error Enable Bit 0: Ignore baud rate errors 1: Check baud rate errors SSC0 Automatic Reset Enable Bit 0: No additional action upon a baud rate error 1: The SSC is automatically reset upon a baud rate error SSC0 Master Select Bit 0: Slave Mode. Operate on shift clock received via SCLK. 1: Master Mode. Generate shift clock and output it via SCLK. SSC0 Enable Bit = `0' Transmission and reception disabled. Access to control bits. SSC0BEN SSC0AREN SSC0MS SSC0EN Users Manual 7 - 96 2000-06-15 SDA 6000 Peripherals SSC0EN = 1: Operating Mode SSCCON Reset Value: 0000H 15 14 13 - 12 11 10 9 8 7 - 6 - 5 - 4 - 3 2 1 0 SSC0 SSC0 EN MS SSC0 SSC0 SSC0 BSY BE PE SSC0 SSC0 RE TE SSC0BC rw rw r rw rw rw rw rw Bit SSC0BC SSC0TE SSC0RE SSC0PE SSC0BE Function SSC0 Bit Count Field Shift counter is updated with every shifted bit. Do not write to!!! SSC0 Transmit Error Flag 1: Transfer starts with the slave's transmit buffer not being updated SSC0 Receive Error Flag 1: Reception completed before the receive buffer was read SSC0 Phase Error Flag 1: Received data changes around sampling clock edge SSC0 Baud Rate Error Flag 1: More than factor 2 or 0.5 between Slave's actual and expected baud rate SSC0 Busy Flag Set while a transfer is in progress. Do not write to!!! SSC0 Master Select Bit 0: Slave Mode. Operate on shift clock received via SCLK. 1: Master Mode. Generate shift clock and output it via SCLK. SSC0 Enable Bit = `1' Transmission and reception enabled. Access to status flags and M/S control. SSC0BSY SSC0MS SSC0EN Note: The target of an access to SSCCON (control bits or flags) is determined by the state of SSC0EN prior to the access, i.e. writing C057H to SSC0CON in programming mode (SSC0EN = `0') will initialize the SSC (SSC0EN was `0') and then switch it on (SSC0EN = `1'). When writing to SSCCON, make sure that zeros are input to reserved locations. The SSC0 baud rate timer reload register SSCBR contains the 16-bit reload value for the baud rate timer. Users Manual 7 - 97 2000-06-15 SDA 6000 Peripherals SSCBR 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SSC0RL(15 ..0) rw Bit SSC0RL (15 ... 0) Function Baud Rate Timer/Reload Register Value Reading SSCBR returns the 16-bit content of the baud rate timer. Writing SSC0BR loads the baud rate timer reload register. The SSC0 transmitter buffer register SSCTB contains the transmit data value. SSCTB 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SSC0TD(15..0) rw Bit SSC0TD (15 ... 0) Function Transmit Data Register Value SSCTB contains the data to be transmitted. Unselected bits of SSC0TB are ignored during transmission. The SSC0 receiver buffer register SSCRB contains the receive data value. Users Manual 7 - 98 2000-06-15 SDA 6000 Peripherals SSCRB 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 SSC0RD(15..0) r Bit SSC0RD (7 ... 0) Function Receive Data Register Value SSCRB contains the received data bits. Unselected bits of SSC0RB will be not valid and should be ignored 7.5 I2C-Bus Interface The on-chip I2C Bus module connects the M2 to other external controllers and/or peripherals via the two-line serial I2C interface. The I2C Bus module provides communication at data rates of up to 400 Kbit/s and features 7-bit as well as 10-bit addressing. The module can operate in three different modes: Master mode, where the I2C controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus transactions and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the I2C can be master or slave. The on-chip I2C bus module allows efficient communication via the common I2C bus. The module unloads the CPU of low level tasks such as * * * * * (De)Serialization of bus data. Generation of start and stop conditions. Monitoring the bus lines in slave mode. Evaluation of the device address in slave mode. Bus access arbitration in multimaster mode. Features * * * * Extended buffer allows up to 4 send/receive data bytes to be stored. Support of standard 100 KBaud and extended 400 KBaud data rates. Operation in 7-bit or 10-bit addressing mode. Flexible control via interrupt service routines or by polling. Users Manual 7 - 99 2000-06-15 SDA 6000 Peripherals 7.5.1 Operational Overview Data is transferred by the 2-line I2C bus (SDA, SCL) using a protocol that ensures reliable and efficient transfers. This protocol clearly distinguishes regular data transfers from defined control signals which control the data transfers. The following bus conditions are defined: Bus Idle: Data Valid: SDA and SCL remain high. The I2C bus is currently not used. SDA stable during the high phase of SCL. SDA then represents the transferred bit. There is one clock pulse for each transferred bit of data. During data transfers SDA may only change while SCL is low (see below)! Start Transfer: A falling edge on SDA ( ) while SCL is high indicates a start condition. This start condition initiates a data transfer over the I2C bus. Stop Transfer: A rising edge on SDA ( ) while SCL is high indicates a stop condition. This stop condition terminates a data transfer. An arbitrary number of bytes may be transferred between a start condition and a stop condition. 7.5.2 The Physical I2C-Bus Interface Communication via the I2C Bus uses two bidirectional lines, the serial data line SDA and the serial clock line SCL. Each of these two generic interface lines can be connected to a number of IO port lines. These connections can be established and released under software control. SDAx Generic Data Line SDA0 2 C Module Generic Clock Line SCL0 SCLx UES11164 Figure 7-45 I2C Bus Line Connections Users Manual 7 - 100 2000-06-15 SDA 6000 Peripherals This mechanism allows a number of configurations of the physical I2C Bus interface: Physical Channels Can be selected, so the I2C module can use electrically separated channels or increase the addressing range by using more data lines. Note: Baud rate and physical channels should never be changed (via ICCFG) during a transfer. Channel Switching The I2C module can be connected to a specific pair of pins (e.g. SDA0 and SCL0) which then forms a separate I2C channel to the external system. The channel can be dynamically switched by connecting the module to another pair of pins (e.g. SDA1 and SCL1). This establishes physically separate interface channels. Broadcasting: Connecting the module to more than one pair of pins (e.g. SDA0/1 and SCL0/1) allows the transmission of messages over multiple physical channels at the same time. Please note that this configuration is critical when the M2 is a slave. In master mode it cannot be guaranteed that all selected slaves have reached the message. Register ICCFG selects the bus baud rate as well the activation of SDA and SCL lines. So an external I2C channel can be established (baud rate and physical lines) with one single register access. Note: Respective port pin definition Users Manual 7 - 101 2000-06-15 SDA 6000 Peripherals SDA SCL 2 C-Channel 0 SDA 6000 2 C-Bus Node 2 C-Bus Node SDA SCL 2 C-Channel 1 UES11165 Figure 7-46 Physical Bus Configuration Example Output Pin Configuration The pin drivers that are assigned to the I2C channel(s) provide open drain outputs (i.e. no upper transistor). This ensures that the I2C module does not put any load on the I2C bus lines while the M2 is not powered. The I2C bus lines therefore require external pull-up resistors (approx. 10 K for operation at 100 KBaud, 2 K for operation at 400 KBaud). All pins of the M2 that are to be used for I2C bus communication must be switched to output, opendrain and their alternate function must be enabled (by setting the respective port output latch to `1'), before any communication can be established. If not driven by the I2C module (i.e. the corresponding enable bit in register ICCFG is `0') they then switch off their drivers (i.e. driving `1' to an open drain output). Due to the external pull-up devices the respective bus levels will then be `1' which is idle. The I2C module features digital input filters in order to improve the noise output from the external bus lines. Users Manual 7 - 102 2000-06-15 SDA 6000 Peripherals 7.5.3 Functional Overview Operation in Master Mode If the on-chip I2C module controls the I2C bus (i.e. bus master), master mode must be selected via bit field MOD in register ICCON. The physical channel is configured by a control word written to register ICCFG, defining the active interface pins and the used baud rate. More than one SDA and/or SCL line may be active at a time. The address of the remote slave that is to be accessed is written to ICRTB0 ... 3. The bus is claimed by setting bit BUM in register ICCON. This generates a start condition on the bus and automatically starts the transmission of the address in ICRTB0. Bit TRX in register ICCON defines the transfer direction (TRX = `1', i.e. transmit, for the slave address). A repeated start condition is generated by setting bit RSC in register ICCON, which automatically starts the transmission of the address previously written to ICRTB0. This may be used to change the transfer direction. RSC is cleared automatically after the repeated start condition has been generated. The bus is released by clearing bit BUM in register ICCON. This generates a stop condition on the bus. Note: Between load the address in ICRTB0 an setting bit BUM at least one command (nop) has to be executed. Operation in Multimaster Mode If multimaster mode is selected via bit field MOD in register ICCON, the on-chip I2C module can operate concurrently as a bus master or as a slave. The descriptions of these modes apply accordingly. Multimaster mode implies that several masters are connected to the same bus. As more than one master may try to claim the bus at a given time, an arbitration is done on the SDA line. When a master device detects a mismatch between the data bit to be sent and the actual level on the SDA (bus) line, it looses the arbitration and automatically switches to slave mode (leaving the other device as the remaining master). This loss of arbitration is indicated by bit AL in register ICST which must be checked by the driver software when operating in multimaster mode. Lost arbitration is also indicated when the software tries to claim the bus (by setting bit BUM) while the I2C bus is active (indicated by bit BB = `1'). Bit AL must be cleared via software. Operation in Slave Mode If the on-chip I2C module is controlled via the I2C bus by a remote master (i.e. be a bus slave), slave mode must be selected via bit field MOD in register ICCON. The physical channel is configured by a control word written to register ICCFG, defining the active interface pins and the used baud rate. It is recommended to have only one SDA and SCL Users Manual 7 - 103 2000-06-15 SDA 6000 Peripherals line active at a time when operating in slave mode. The address by which the slave module can be selected is written to register ICADR. The I2C module is selected by another master when it receives (after a start condition), either its own device address (stored in ICADR) or the general call address (00H). In this case an interrupt is generated and bit SLA in register ICST is set, indicating the valid selection. The desired transfer mode is then selected via bit TRX (TRX = `0' for reception, TRX = `1' for transmission). For a transmission the respective data byte is placed into the buffer ICRTB0 ... 3 (which automatically sets bit TRX) and the acknowledge behavior is selected via bit ACKDIS. For a reception the respective data byte is fetched from the buffer ICRTB0 ... 3 after IRQD has been activated. In both cases the data transfer itself is enabled by clearing bits IRQD, IRQP and IRQE which releases the SCL line. When a stop condition is detected, bit SLA is cleared. The I2C bus configuration register ICCFG selects the bus baud rate (partly) as well as the activation of SDA and SCL lines. So an external I2C channel can be established (baud rate and physical lines) with one single register access. Systems that utilize several I2C channels can prepare a set of control words which configure the respective channels. By writing one of these control words to ICCFG the respective channel is selected. Different channels may use different baud rates. Also different operating modes can be selected, e.g. enabling all physical interfaces for a broadcast transmission. Note: Refer also to Chapter 7.5.2. Users Manual 7 - 104 2000-06-15 SDA 6000 Peripherals 7.5.4 Registers All available module registers are summarized in the overview table below. Register Name ICCFG ICCON ICST ICADR ICRTBL ICRTBH IICPISEL2) 1) 2) Register Description I2C Configuration Register I2C Control Register I C Status Register I C Address Register I C Receive/Transmit Buffer I2C Receive/Transmit Buffer I2C Port Input Select Register 2 2 2 Address b/p1) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00'E810H b 00'E812H b 00'E814H b 00'E816H b 00'E818H - 00'E81AH - 00'E804H b b: bit addressable / p: bit protected Itus currently no function. Should be left on reset value. I2C Configuration Register ICCFG 15 14 13 12 11 10 9 8 7 0 6 0 5 SCL EN1 4 SCL EN0 Reset Value: 0000H 3 0 2 1 0 BRPL SDA SDA SDA EN2 EN1 EN0 Field SDAENx (x = 2 ... 0) Bits 2...0 Type rw Value Description Enable Input for Data Pin x These bits determine to which pins the I2C data line is connected. SDA pin x is disconnected. SDA pin x is connected with I2C data line. Enable Input for Clock Pin x These bits determine to which pins the I2C clock line is connected. SCL pin x is disconnected. SCL pin x is connected with I2C clock line. Baud rate Prescaler Low Determines the 8 least significant bits of the 10 bit baud rate prescaler. (See BPRH in ICADR.) 7 - 105 2000-06-15 0 1 SCLENx (x = 3 ... 0) 5...4 rw 0 1 BRPL 15 ... 8 rw - Users Manual SDA 6000 Peripherals I2C Control Register ICCON 15 WM EN 14 13 12 11 10 9 8 7 6 5 ACK DIS 4 BU M Reset Value: 0000H 3 2 1 0 0 0 0 CI STP IGE TRX INT MOD RSC M10 Field M10 Bits 0 Type rw Value 0 1 Description Address Mode 7-bit addressing using ICA7 ... 1. 10-bit addressing using ICA9 ... 0. Repeated Start Condition No operation. Generate a repeated start condition in (multi) master mode. RSC cannot be set in slave mode. Note: RSC is cleared automatically after the repeated start condition has been sent. Basic Operating Mode I2C module is disabled and initialized (InitMode). Transmissions under execution will be aborted. Slave mode. 10 Master mode. 11 Multi-Master mode. Busy Master Clearing bit BUM ( ) generates a stop condition immediately. Setting bit BUM ( ) generates a start condition in (multi)master mode. Note: Setting bit BUM ( ) while BB = `1' generates an arbitration lost situation. In this case BUM is cleared and bit AL is set. BUM can not be set in slave mode. RSC 1 rwh 0 1 MOD [3:2] rwh 00 01 10 11 BUM 4 rwh 0 1 Users Manual 7 - 106 2000-06-15 SDA 6000 Peripherals Field ACKDIS Bits 5 Type rwh 0 1 Value Description Acknowledge Pulse Disable An acknowledge pulse is generated for each received frame. No acknowledge pulse is generated. Note: ACKDIS is automatically cleared by a stop condition. Interrupt Delete Select Interrupt flag IRQD is deleted by read/write to ICRTB0 ... 3. Interrupt flag IRQD is not deleted by read/ write to ICRTB0 ... 3. Transmit Select No data is transmitted to the I2C bus. Data is transmitted to the I2C bus. Note: TRX is set automatically when writing to the transmit buffer. It is not allowed to delete this bit in the same buscycle. It is automatically cleared after last byte as slave transmitter. Ignore IRQE Ignore IRQE (End of transmission) interrupt. The I2C is stopped at IRQE interrupt. The I2C ignores the IRQE interrupt. If RMEN is set, RM is mirrored here. Stop Master 0 Clearing bit STP generates no stop condition. 1 Setting bit STP generates a stop condition after next transmission. BUM is set to zero. ACKDIS is set to one. STP is automatically cleared by a stop condition. If RMEN is set, RM is mirrored here. INT 6 rw 0 1 TRX 7 rwh 0 1 IGE 8 rw 0 1 STP 9 rwh 0 1 Users Manual 7 - 107 2000-06-15 SDA 6000 Peripherals Field CI Bits Type Value 00 01 10 11 WMEN 15 rwh 0 1 Description Length of the Transmit Buffer 1 Byte 2 Bytes 3 Bytes 4 Bytes If RMEN is set, RM is mirrored here. Write Mirror Enable write mirror is not active write mirror is active If RMEN is set WMEN can not be set and will remain zero. If WMEN and RMEN are simultaneously set to 1, both will remain what they are. So only one of each can be set to 1. RM [15:8] rw - Read Mirror If RMEN is set, RTB0 may be read here. Writing to RM has no effect in this mode. [10:9] rw Users Manual 7 - 108 2000-06-15 SDA 6000 Peripherals I2C Status Register ICST 15 RM EN 14 0 13 0 12 0 11 0 10 9 CO 8 7 IRQ E 6 IRQ P 5 IRQ D 4 BB Reset Value: 0000H 3 LRB 2 SLA 1 AL 0 ADR Field ADR Bits 0 Type rh Value Description - Address Bit ADR is set after a start condition in slave mode until the address has been received (1 byte in 7-bit address mode, 2 bytes in 10-bit address mode). Arbitration Lost Bit AL is set when the I2C module has tried to become master on the bus, but has lost the arbitration. Operation is continued until the 9th clock pulse. If multimaster mode is selected the I2C module temporarily switches to slave mode after a lost arbitration. Bit IRQP is set along with bit AL. AL must be cleared via software. Slave The I2C module is not selected as a slave, or the module is in master mode. The I2C module has been selected as a slave (device address received). Last Received Bit Bit LRB represents the last bit (i.e. the acknowledge bit) of the last transferred frame. It is automatically set to zero by a write or read access to the buffer ICRTB0 ... 3. Note: If LRB is high (no acknowledge) in slave mode, TRX bit is set automatically. AL 1 rwh - SLA 2 rh 0 1 LRB 3 rh - Users Manual 7 - 109 2000-06-15 SDA 6000 Peripherals Field BB Bits 4 Type rh 0 1 Value Description Bus Busy The I2C bus is idle, i.e. a stop condition has occurred. The I2C bus is active, i.e. a start condition has occurred. Note: Bit BB is always `0' while the I2C module is disabled. I2C Interrupt Request Bit for Data Transfer Events 1) No interrupt request pending. A data transfer event interrupt request is pending. IRQD is set after the acknowledge bit of the last byte has been received or transmitted, and is cleared automatically upon a complete read or write access to the buffer(s) ICRTB0 ... 3. New data transfers will start immediately after clearing IRQD. Do not access any register until next interrupt. If in polling mode and CI is `0' only 8-Bit accesses to the lower byte are allowed. Note: If a multi byte write could not be finished in slave mode because of missing acknowledge, then the data interrupt is followed by a end of transmission interrupt. The number of bytes sent can be read from CO. The data interrupt must have higher priority than IRQE. IRQD 5 rwh 0 1 Users Manual 7 - 110 2000-06-15 SDA 6000 Peripherals Field IRQP Bits 6 Type rwh 0 1 Value Description I2C Interrupt Request Bit for Protocol Events 1) No interrupt request pending. A protocol event interrupt request is pending. IRQP is set when bit SLA or bit AL is set ( ), and must be cleared via software. If the I2C has been selected by an other master, the software must look up the required transmission direction by reading the received address and direction bit, stored in ICRTB0. The TRX-bit must correspondingly be set by software. I2C Interrupt Request Bit for Data Transmission End 1) No interrupt request pending. A receive end event interrupt request is pending (a stop is detected). IRQE is automatically cleared upon a start condition. IRQE is not activated in init-mode. IRQE must always be deleted to continue transmission. Note: In slave mode IRQE is set after the transmission is finished. This can also be after a stop or RSC condition. In this case the slave is not selected any more. This bit is also set, if a transmission is stopped by a missing acknowledge. In this case the bit must be cleared by software. IRQE 7 rwh 0 1 Users Manual 7 - 111 2000-06-15 SDA 6000 Peripherals Field CO Bits Type Value Description Counter of Transmitted Bytes Since Last Data Interrupt. If a multi byte transmission could not be finished because of a missing acknowledge, the number of correctly transferred bytes can be read from CO. It is automatically set to zero by the correct number (defined by CI) of write/read accesses to the buffers ICRTB0 ... 3. No Byte 1 Byte 2 Bytes 3 Bytes 4 Bytes The number of legal bytes depends on the data buffer size (CI). Writing to this bit field does not affect its content. If WMEN is set, WM is mirrored here. Write Mirror If WMEN is set, RTB0 may be written here. Reading WM will result in zero. 10..8 rw 000 001 010 011 100 WM [15:8] wh - 1) While IRQD, IRQP or IRQE is set and the I2C module is in master mode or has been selected as a slave, the I2C clock line is held low which prevents further transfers on the I2C bus. The clock line of the I2C bus is released when IRQD, IRQE and IRQP are cleared. Only in this case can the next I2C bus action take place. Interrupt request bits may be set or cleared via software, e.g. to control the I2C bus. Users Manual 7 - 112 2000-06-15 SDA 6000 Peripherals I2C Address Register ICADR 15 BRP MO D 14 13 12 0 11 0 10 0 9 ICA 9/ 0 8 ICA 8 IGE 7 6 5 4 ICA7..1 Reset Value: 0000H 3 2 1 0 ICA 0/ 0 PREDIV Field ICA0 Bits 0 Type rw Value Description - Node Address Bit 0 in 10-Bit Mode (See ICCON bit M10) Access is only possible in 10-bit mode. Reserved read/write 0 if in 7-bit mode. Node Address in 7-Bit Mode (ICA9 and ICA0 disregarded, ICA8 becomes IGE-bit). Ignore IRQE In 7-bit mode, this bit becomes IGE-bit: Ignore IRQE (End of transmission) interrupt. The I2C is stopped at IRQE interrupt. The I2C ignores the IRQE interrupt. Access is only possible in 7-bit mode. Node Address Bit 8 in 10-Bit Mode Access is only possible in 10-bit mode. Node Address in 10-Bit Mode (all bits used). Note: Access is only possible in 10-bit mode. Pre Divider for Baud Rate Generation pre divider is disabled pre divider factor 8 is enabled pre divider factor 64 is enabled reserved, do not use Baud Rate Prescaler Mode Mode 0 is enabled (by default) Mode 1 is enabled. - ICA7 ... 1 IGE 0 7..1 8 0 rw rw 0 - 0 1 ICA8 ICA9..0 8 9..0 rw rw - - PREDIV [14:13] rw 00 01 10 11 BRPMOD 15 rw 0 1 Baud Rate Selection In order to give the user high flexibility in selection of CPU frequency and baud rate, without constraints to baud rate accuracy, a flexible baud rate generator has been Users Manual 7 - 113 2000-06-15 SDA 6000 Peripherals implemented. It uses two different modes and an additional pre divider. Low baud rates may be configured at high precision in mode 0 which is compatible with older versions. High baud rates may be configured precisely in mode 1. Mode 0: Reciprocal Divider The resulting baud rate is cpu B IIC = ---------------------------------4 ( BRP + 1 ) f cpu BRP = ----------------- - 1 4 B IIC f Mode 1: Fractional Divider The resulting baud rate is f cpu BRP B IIC = ----------------------------1024 Table 7-24 BRPMOD 1024 B IIC BRP = --------------------------- f cpu I2C-Bus Baud Rate Selection @ 33.33 MHz CPU-Freq. BRP @ 100 kBaud PREDIV = 00B PREDIV = 01B 0AH - PREDIV = 10B 1H - BRP @ 400 kBaud PREDIV = 00B 14H 0CH PREDIV = 01B 02H 02H PREDIV = 10B - - 0 1 52H 03H Users Manual 7 - 114 2000-06-15 SDA 6000 Peripherals I2C Receive/Transmit Buffer ICRTBH/L 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ICRTB3 ICRTB2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICRTB1 ICRTB0 Field ICRTBx x= 3...0 Bits Type Value - Description Receive/Transmit Buffer 1) 2) The buffers contain the data to be sent/ received. The buffer size can be set in bit field CI (from 1 up to 4 bytes). ICRTB0 is sent/ received first. 15..0 rwh 1) A read respectively a write access (depending on bit TRX) to all bytes (specified in CI) of ICRTB0 ... 3 sets CO to 111 (no byte sent/received). If bit INT is set to zero and all bytes (specified in CI) of ICRTB0 ... 3 are read/written (depending on bit TRX) IRQD is cleared. 2) Users Manual 7 - 115 2000-06-15 SDA 6000 Peripherals Interrupts Table 7-25 Interrupt Data Interrupt Sources SRC Register I2CTIC Description Interrupt is requested after the acknowledge bit of the last byte has been received or transmitted. Interrupt is requested if a multi byte write could not be finished in slave mode because of missing acknowledge, then the data interrupt is followed by an end of transmission interrupt. Interrupt is requested when the I2C module has tried to become master on the bus but has lost the arbitration. Interrupt is requested if multimaster mode is selected and the I2C module temporarily switches to slave mode after a lost arbitration. Interrupt is requested if multimaster mode is selected and the I2C module temporarily switches to slave mode after a lost arbitration. Interrupt is requested after transmission is finished by a stop condition. Interrupt is requested after transmission is finished by a repeated start condition (RSC). Interrupt is also requested if a transmission is stopped by a missing acknowledge. Data Error I2CTIC Protocol: Arbitration Lost I2CPIC Protocol: Slave Mode after Lost Arbitration I2CPIC Protocol: Slave Mode after Device Address I2CPIC Data Trans-mission End after Stop Condition Data Trans-mission End after RSC Condition I2CTEIC I2CTEIC Data Transmission End after I2CTEIC missing Acknowledge Users Manual 7 - 116 2000-06-15 SDA 6000 Peripherals Synchronization In Mastermode, the SCL line is controlled by the I2C Module. Sent and received data is only valid if SCL is high. With SCL going down, all modules are starting to count down their low period. During the low period all connected modules are allowed to hold SCL low. As the physical bus connection is wired-AND, SCL will remain low until the device with the longest low period enters high state. Then the device with the shortest high period will pull SCL low again. Programming It is strictly recommended not to write to the I2C registers when the I2C is working, except for interrupt handling. This is indicated by the BUM bit (in master mode) and the interrupt flags. All registers can be written in initial mode. In master mode the I2C is working as long as the BUM bit is set, in slave mode the I2C is working from receiving a start condition until receiving the next stop condition. Change of transmit direction is possible only after a protocol interrupt (IRQP) or in initialization mode (MOD = 00B). Initialization Before data can be sent or received, data buffer size must be set in the count registers (only necessary if buffer greater than one byte is available). To decide if slave/master or multimaster mode is required, the MOD bits must be programmed. Repeated Start Condition The RSC bit must be set to one. Start Condition To generate a start condition the I2C must be in master mode. If the BUM bit is set, a start condition is sent and the transmission started. The slave returns the acknowledge bit, which is indicated by the LRB bit. Sending Data Bytes To send bytes it is only necessary to write data bytes to the transmit buffer every time a data interrupt (IRQD) occurs. Stop Condition The BUM bit must be set to zero, or the STP bit must be set to one. Receiving Data Bytes To receive bytes it is necessary to set the TRX bit to zero. The bytes can be read after every data interrupt (IRQD). After a stop condition (protocol interrupt IRQE), the count Users Manual 7 - 117 2000-06-15 SDA 6000 Peripherals bit field CO must be read in case the buffer size (defined in CI) is greater than one byte, to decide which bytes in the receive buffer were received in the last transmission cycle. 7.6 Analog Digital Converter M2 includes a four channel 8-bit ADC for control purposes. By means of these four input signals the controller is able to supervise the status of several analog signals and to take action if necessary. As these analog signals are fairly slow (compared to the video input), one SAR-Converter is used. The input is multiplexed to four different analog inputs. The ADC is running continuously. The four channels are scanned one after another. The conversion results (one byte per channel), for the four channels, are stored in registers ADDAT1 and ADDAT2. After completion of the conversion for the last channel, two interrupt request flags ADC1IR and ADC2IR are generated. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in the memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. The S&H circuit is open for about 2 s. New results are available in ADDAT1 and ADDAT2 every 48 s. The previous conversion results are overwritten unless the contents are transferred to the memory by PEC data transfers or an ordinary interrupt service routine. If some of the port lines P5.0 to P5.3 are to be used as digital inputs the associated enable bits in register P5BEN have to be enabled. The input voltage on port 5 should never exceed 2.5 V. A set of SFRs and port pins provide access to control functions and results of the ADC. Ports & Direction Control Alternate Functions Data Registers Control Registers Interrupt Control P5 AN0/P5.0 ... AN3/P5.3 ADDAT1 ADDAT2 ADCON AD1IC AD2IC P5 Port 5 Data Register ADDAT1 A/D Converter Result Register 1 ADDAT2 A/D Converter Result Register 2 AD1IC A/D Converter Interupt Control Register (end of conversion) AD2IC A/D Converter Interrupt Control Register (end of conversion) UEA11166 Figure 7-47 SFRs and Port Pins Associated with the A/D Converter Users Manual 7 - 118 2000-06-15 SDA 6000 Peripherals 7.6.1 Power Down and Wake Up As the power consumption of the ADC is quite high it should also be switched off during idle mode. Due to some application requirements it is necessary to include the possibility of generating an interrupt signal (ADWIC) as soon as the CADC (ANA0) input voltage falls below a predefined level. Two different levels are available. The first one corresponds to (fullscale-4 LSB) the second one to (fullscale-16 LSB). The actual level can be selected by a control bit (ADWULE). 7.6.2 ADCON 15 - Register Description Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 FS ADC DIFF 4 ADWUL E 3 - 2 - 1 - 0 - rw rw Bit Function FSADCDIFF Selects FSADC input range Selects input range of the Full Service ADC: FSADCDIFF = 0: single-ended input FSDACDIFF = 1: differential input ADWULE Defines threshold level for wake up A special wake up unit has been implemented to allow a system wake-up as soon as the analog input signal on pin ANA0 falls below a predefined level. ADWULE defines this level. ADWULE = 0: threshold level corresponds to fullscale-4LSB. ADWULE = 1: threshold level corresponds to fullscale-16LSB. Reset Value: 0000H 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDAT1 15 14 ADRES1 ADRES0 rw rw Users Manual 7 - 119 2000-06-15 SDA 6000 Peripherals ADDAT2 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0000H 3 2 1 0 ADRES3 ADRES2 rw rw Bit ADRESi (7 ... 0) Function A/D Conversion Result (8-bit) of Channel 0 ... 3 (ANA 0 ... 3) For each A/D channel two successive 7-bit samples (@33.3 MHZ) are processed, averaged and scaled to 0 - 254. Users Manual 7 - 120 2000-06-15 Clock System SDA 6000 Clock System 8 8.1 Clock System General Function The on-chip clock generator provides M2 with its basic clock signals. Its oscillator can either run with an external crystal and appropriate oscillator circuitry (refer to "Application Diagram") or it can be driven by an external digital clock signal. For applications with low accuracy requirements (RTC is not used) the external oscillator circuit can also be a ceramic resonator. Depending on the absolute tolerance of the resonator the slicer may not work correctly. Moreover the display timings and baud rate prescaler have to be adapted in an appropriate way. In some applications the timing reference given by the horizontal frequency of the CVBS signal can be used to measure the timing tolerance and to adjust the programming. RTC /6 fCPU 33.33 MHz 3 MHz /2 C C-Periph. Ports Sync ADC Slicer XTAL1 XTAL2 OSC 6 MHz PLL /2 200 MHz (/ 3) fEMI 100 MHz 66.7 MHz 3 MHz EBI DG CLUTs 300 MHz fPIX 10 MHz DTO 50 MHz Display-FIFO SRU (part 2) DAC UES11167 Figure 8-1 Clock System in M2 The on-chip phase locked loop (PLL), which is internally running at 600 MHz, is fed by the oscillator or can be bypassed to reduce the power consumption in idle and sleep mode. If it is not required to wake up immediately from idle mode, the PLL can be Users Manual 8-3 2000-06-15 SDA 6000 Clock System switched off by entering sleep-mode. The same oscillator is used to clock the built-in RTC. (For a further description refer to Chapter 7.2.) From the output frequency of the PLL three clock systems are derived: One, the 33 MHz system clock (fCPU) supplies the processor, all processor related peripherals, the sync timing logic, the A/D converters and the slicer. The second clock system (100/66 MHZ) (fEBI) is used to clock the external bus interface, the display generator, the CLUTs and the input part of the display FIFO. This clock starts at 66 MHz after hardware reset. It can be configured to 100 MHz during the initialization sequence. The frequency of the latter clock system can be changed via bit CLKCON in register SYSCON2. The refresh rate of the external SDRAM is always kept constant, independent of the selected system clock frequency. The third clock system runs the pixel clock (fPIX), which is programmable in a range of 10 ... 50 MHz. It serves the output part of the display FIFO and the D/A converters. The pixel clock is derived from the high frequency output of the PLL and it is phase shifted line by line to the positive edge of the horizontal sync signal (normal polarity). Because the final display clock is derived from a DTO (digital time oscillator) it has no equidistant clock periods although the average frequency is exact. This pixel clock generation system has several advantages: * The frequency of the pixel clock can be programmed independently from the horizontal line period. * Since the input of the PLL is already a signal with a high frequency, the resulting pixel frequency has an extremely low jitter. * The resulting pixel clock follows the edge of the H-sync impulse without any delay and always has the same quality as the sync timing of the deflection controller. 8.2 SYSCON2 15 1 Register Description Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 - 8 CLK CON 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - r rw Bit CLKCON Function Bus Clock Frequency 0: fEBI = 66 MHz 1: fEBI = 100 MHz Users Manual 8-4 2000-06-15 SDA 6000 Clock System Note: Register SYSCON2 cannot be changed after execution of the EINIT instruction. PFR 15 - Reset Value: 0148H 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 PF(10..0) 4 3 2 1 0 rw Bit PF (10 ... 0) Function Pixel Frequency Factor This register defines the relation between the output pixel frequency and the frequency of the crystal. The pixel frequency does not depend on the line frequency. It can be calculated by the following formula: fPIX = PF x 300 MHz / 8192 The pixel frequency can be adjusted in steps of 36.6 KHz. After power-on, this register is set to 328D. So, the default pixel frequency is set to 12.01 MHz. Note: Register values exceeding 1366 generate pixel frequencies which are outside of the specified boundaries. Users Manual 8-5 2000-06-15 Sync System SDA 6000 Sync System 9 9.1 Sync System General Description The display sync system is completely independent of the acquisition sync system (CVBS timing) and can either work as a sync master or as a sync slave system. Any mention of "H/V-Syncs" in this chapter and in Chapter 10 always refers to display related H/V Syncs and never to CVBS related sync timing. In sync slave mode, M2 receives the synchronisation information from two independent pins which deliver separate horizontal and vertical signals. Due to the not-line-locked pixel clock generation (refer to Chapter 8), it can process any possible horizontal and vertical sync frequency. In sync master mode, M2 delivers separate horizontal and vertical signals with the same flexibility in the programming of their periods as in sync slave mode. 9.1.1 Screen Resolution The number of displayable pixels on the screen is defined by the pixel frequency (which is independent of horizontal frequency), the line period and number of lines within a field. The screen is divided into 3 different regions: Users Manual 9-3 2000-06-15 SDA 6000 Sync System EVCR BVCR Vertical Blacklevel Clamping Screen Background Area Horizontal Blacklevel Clamping V-Sync Delay (SDV) H-Sync Delay (SDH) Pixel Layer 1 Variable Height Pixel Layer 2 Variable Width VLR t H_clmp_b (BHCR) t H_clmp_e (EHCR) t H_period (HPR) H-Sync UET11168 Figure 9-1 M2's Display Timing Blacklevel Clamping Area During horizontal and vertical blacklevel clamping, the black value (RGB = 000) is delivered. The blank pin is set to `1' and COR is set to `0' (normal polarity assumed). This area is vertically programmable (in terms of lines) and horizontally in terms of 33.33 MHz clock cycles. These programmings are independent of all other registers. Screen Background Area The size of that area is defined by the sync delay registers (SDH and SDV) and the size of pixel layer1. The contents of that area are defined by GA instruction SAR (refer also to Chapter 10.1). Pixels within that area are programmable (colour and transparency level), but all have the same value. Users Manual 9-4 2000-06-15 SDA 6000 Sync System Pixel Layer Area Pixels of this area are freely programmable according to the specifications of the display generator. The information is stored in the frame buffer in the external memory, that means the bigger that area is defined, the more bus performance is needed for SRU. If that area is set to `0' no bus performance is needed. The start position of that area can be shifted in horizontal and vertical direction by programming the horizontal and vertical sync delay registers (SDH and SDV). The size of that area is defined by the instruction FSR in the display generator. Registers which allow the screen and sync parameters to be set up, are given in the Table 9-1. Table 9-1 Parameters Sync Control Register VL - Lines / Field Th-period - Horizontal Period Fpixel - Pixel Frequency Tvsync_delay - Sync Delay Thsync_delay - Sync Delay BVCR - Beginning Of Vertical Clamp Phase EVCR - End Of Of Vertical Clamp Phase Th_clmp_b - Beginning Of Horizontal Clamp Phase Overview on Sync Register Settings Register SCR VLR HPR PFR SDV SDH BVCR EVCR BHCR 1 line 15 s 10 MHz 4 lines 32 pixel 1 line 1 line 0 s 0 s Min Value Max Value Step Default see below 1024 lines 1 line 100 s 50 MHz 30 ns 73.25 KHz 625 lines 64 s 12.01 MHz 32 lines 72 pixel line 1 line 5 0 s 4.5 s 1024 lines 1 line 2048 pixel 1 pixel 1024 lines 1 line 1024 lines 1 line 163.2 s 163.2 s 480 ns 480 ns Th_clmp_e - End EHCR Of Horizontal Clamp Phase 9.1.2 Sync Interrupts The sync unit delivers interrupts (Horizontal and vertical interrupt) to the controller to support the recognition of the frequencies of an external sync source (e.g. a VGA source via SCART). These interrupts are related to the positive edge of the non delayed horizontal and vertical impulses which can be seen at pins HSYNC and VSYNC. Users Manual 9-5 2000-06-15 SDA 6000 Sync System 9.2 SCR 15 - Register Description Reset Value: 0000H 14 - 13 - 12 - 11 CORBL 10 9 8 7 6 BLAN KP 5 COR P 4 HP 3 VP 2 INT 1 VCS 0 MAST VSU(3..0) rw Bit MAST Function rw rw rw rw rw rw rw rw Master / Slave Mode This bit defines the configuration of the sync system (master or slave mode) and also the direction (input/output) of the V, H pins. 0: Slave mode. H, V pins are configured as inputs. 1: Master mode. H, V pins are configured as outputs. Note: Switching from slave to master mode resets the internal H, V counters, so that the phase shift during the switch can be minimized. In slave mode registers VLR, and HPR are without any use. VCS Vertical Composite Sync VCS defines the sync output at pin V (Master mode only). 0: At pin V the vertical sync appears. 1: At pin V a composite sync signal (including equalizing pulses, HSync and V-Syncs) is generated (VCS). The length of the equalizing pulses have fixed values as described in the timing specifications. Note: Don't forget to set registers VLR and HPR according to your requirements. INT Interlace / Non-interlace M2 can either generate an interlaced or a non-interlaced timing. (Master mode only). Interlaced timing can only be created if VLR is an odd number. 0: Interlaced timing is generated. 1: Non-interlaced timing is generated. V-Pin Polarity This bit defines the polarity of the V pin (master and slave mode). 0: Normal polarity (active high). 1: Negative polarity. VP Users Manual 9-6 2000-06-15 SDA 6000 Sync System Bit HP Function H-Pin Polarity This bit defines the polarity of the H pin. (Master and slave mode). 0: Normal polarity (active high). 1: Negative polarity. COR-Pin Polarity This bit defines the polarity of the COR pin. (Master and slave mode). 0: Normal polarity (active high). 1: Negative polarity (not allowed for CORBL = 1). BLANK-Pin Polarity This bit defines the polarity of the BLANK pin. (Master and slave mode). 0: Negative polarity (not allowed for CORBL = 1). 1: Normal polarity (active high). CORP BLANKP VSU (3 ... 0) Vertical Set Up Time. (Slave mode only) The vertical sync signal is internally sampled with the next edge of the horizontal sync edge. The phase relation between V and H differs from application to application. To guarantee (vertical) jitter free processing of external sync signals, the vertical sync impulse can be delayed before it is internally processed. The following formula shows how to delay the external V-sync before it is internally latched and processed. tV_delay = 3.84 s x VSU CORBL 3-Level Contrast Reduction Output There is one pin each for BLANK and COR. Nevertheless by means of CORBL the user is able to switch the COR signal to a three level signal providing BLANK and contrast reduction information on Pin BLANK simultaneously. 0: Two level signal for contrast reduction. 1: Three level signal Level0: BLANK off; COR off. Level1: BLANK off; COR on. Level2: BLANK on; COR off. Note: Please refer to Chapter 14 for the detailed specification of these levels. Users Manual 9-7 2000-06-15 SDA 6000 Sync System VLR 15 - Reset Value: 0271H 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 3 2 1 0 VL(9..0) rw Bit Function VLR (9 ... 0) Amount of Vertical Lines in a Frame. (Master mode only). M2 generates vertical sync impulses in sync master mode. If, for example, a normal PAL timing should be generated, set the register to `625d' and set the interlace bit to `0'. The hardware will generate a vertical impulse periodically after 312.5 lines. If a non-interlaced picture with 312 lines should be generated, set this register to `312' and set the interlace bit to `1'. The hardware will generate a vertical impulse every 312 lines. Progressive timing can be generated by setting VLR to `625' and interlace to `1'. HPR 15 - Reset Value: 855H 14 - 13 - 12 - 11 10 9 8 7 6 5 4 3 2 1 0 HP(11..0) rw Bit HPR (11 ... 0) Function Horizontal Period factor. (Master mode only) This register allows the period of the horizontal sync signal to be adjusted. The horizontal period is independent of the pixel frequency and can be adjusted with the following resolution: tH-period = HP x 30 ns Users Manual 9-8 2000-06-15 SDA 6000 Sync System SDV 15 - Reset Value: 0020H 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 3 2 1 0 SDV(9..0) rw Bit Function SDV (9 ... 0) Vertical Sync Delay. (Master and slave mode). This register defines the delay (in lines) from the vertical sync to the first line of pixel layer 1 on the screen. SDH 15 - Reset Value: 0020H 14 - 13 - 12 - 11 10 9 8 7 6 SDH 5 4 3 2 1 0 rw Bit SDH (11 ... 0) Function Horizontal Sync Delay. (Master and slave mode). This register defines the delay (in pixels) from the horizontal sync to the first pixel of layer 1 on the screen. Users Manual 9-9 2000-06-15 SDA 6000 Sync System HCR 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: 0A00H 3 2 1 0 EHCR(7..0) EHCR(7..0) rw Bit BHCR (7 ... 0) Function rw Beginning of Horizontal Clamp Phase. (Master and slave mode). This register defines the delay of the horizontal clamp phase from the positive edge of the horizontal sync impulse (normal polarity is assumed). The beginning of the clamp phase can be calculated by the following formula: tH_clmp_b = 480 ns x BHC EHCR (7 ... 0) End of Horizontal Clamp Phase. (Master and slave mode). This register defines the end of the horizontal clamp phase from the positive edge of the horizontal sync impulse (at normal polarity). The end of the clamp phase can be calculated by the following formula: tH_clmp_e = 480 ns x EHC If EHC is smaller than BHC the clamp phase will include the H-sync phase. The clamp phase area has higher priority than the screen background area or the pixel layer area and can be shifted independent from any other register. Users Manual 9 - 10 2000-06-15 SDA 6000 Sync System Clamp Phase Area Screen Background Area Pixel Layer Area Video H Period - Frame n H Pulse UED11169 Figure 9-2 BVCR Priority of Clamp Phase, Screen Background and Pixel Layer Area Reset Value: 0000H BVCR1 BVCR0 15 - 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 3 2 1 0 BVCR(9..0) rw Bit BVCR (9 ... 0) Function Beginning of Vertical Clamp Phase. (Master and slave mode). This register defines the beginning of the vertical clamp phase from the positive edge of the vertical sync impulse (at normal polarity) in line count. Users Manual 9 - 11 2000-06-15 SDA 6000 Sync System EVCR EVCR1 Reset Value: 000AH EVCR0 15 - 14 - 13 - 12 - 11 - 10 - 9 8 7 6 5 4 3 2 1 0 EVCR(9..0) rw Bit EVCR (9 ... 0) Function End of Vertical Clamp Phase. (Master and slave mode). This register defines the end of the vertical clamp phase from the positive edge of the vertical sync impulse (at normal polarity) in line count. Note: It must be guaranteed that the value EVCR is always smaller than the value of SDV. Users Manual 9 - 12 2000-06-15 Display Generator SDA 6000 Display Generator 10 10.1 Display Generator General Description M2's display concept is based on frame buffer technology, which means that for each pixel displayed on a screen appropriate information is stored in the memory of the so called frame buffer. To relieve the controller from processing time consuming tasks like writing this frame buffer pixel by pixel, a graphic accelerator machine is introduced (GA). The GA reads e.g. bitmap information in various formats together with attributes which define the final behavior of those bitmaps. Depending on these attributes these bitmaps are processed and written into the frame buffer. Due to the processor like architecture of the GA, it is controlled by so called GAIs (graphic accelerator instructions). The screen refresh unit (SRU) reads out the pixel based information (various formats are also available here) and hands them over via a look up table and a FIFO to the D/A converter. The FIFO is used to adapt the variable pixel output frequency to the fixed memory bus frequency. Up to two frame buffers are possible and supported by GA and SRU. 10.2 Screen Alignments Two HW-layers are supported: layer 1 and layer 2. Layer 2 can be positioned relative to layer 1 (also in negative direction). If layer 2 exceeds the dimensions of layer 2 these exceeding parts are not visible on the screen. The alignment of the OSD on the screen depends on the configuration of layer 1. The maximum amount of displayable pixels is 2047 pixels in horizontal direction and 1023 pixels in vertical direction. Users Manual 10 - 3 2000-06-15 SDA 6000 Display Generator To adapt M2 to a wide range of displays in the market the sync-processing can be flexibly configured. Vertical Blacklevel Clamping Screen Background Area Horizontal Blacklevel Clamping Layer 2 Area Variable Height Layer 1 Area Non-Visible Part of Layer 2 Variable Width UED11170 Figure 10-1 Display Regions and Alignments There are three registers in the synchronization unit which are necessary for OSD setup: * SDH: used to setup the horizontal position of the top left pixel of layer 1. * SDV: used to setup the vertical position of the top left pixel of layer 1. * PFR: used to setup the pixel frequency. For detailed description of these registers please refer to chapter `Display Sync System' and `Clock System'. In the area which is defined for layer 1 or layer 2 (layer area) each pixel is defined by the attribute definition of the frame buffer. There is no pixel by pixel definition for the blacklevel clamping area and the screen background area. For these areas the colour and transparency is defined as follows: Transparency level and colour of the screen background area is defined globally for the whole screen by GA instruction SAR. During the blacklevel clamping area, black value (RGB = `000') is delivered at RGB output. Pin `Blank' is set to `1' and COR-pin is set to `0' (normal polarity is assumed). Users Manual 10 - 4 2000-06-15 SDA 6000 Display Generator 10.3 Layer Concept M2 supports two HW-layers. Frame buffers of layer 1 and layer 2 can be placed at any word aligned position in external memory. Two different layer modes can be chosen: * Overlapped layers. Layer 1 and layer 2 are processed in parallel by the screen refresh unit. * Embedded layers. Layer 1 and layer 2 are alternatively processed. If the area of layer 2 exceeds the area of layer 1, these parts are not visible on the screen. Mixing of layer 1 and layer 2 is performed by the display generator. As a result of the RGB output of M2, there is only one RGB stream which contains the information of layer 1 and layer 2. This RGB stream is externally mixed with a video source. For this external mixing there are two output signals (COR and BLANK) available. Meshed areas: A special mesh mode is defined to mix the external video with the RGB information from M2 in a chess-pattern-shape. From frame to frame this chess-pattern is inverted. Inverted means, that pixels which have been displayed as video in the previous frame, are displayed as RGB in the following frame. Blank = 1; External Video Blank = 0; RGB of M2 t +2 t+1 t UEA11171 Figure 10-2 Behavior of Blank Pin for Consecutive Frames in `Meshed' Regions Users Manual 10 - 5 2000-06-15 SDA 6000 Display Generator 10.3.1 Overlapped Layers In overlapped layer mode the pixel information of both layers (layer 1, layer 2) is read in parallel to the RAM. This means that for each pixel the individual decision can be made which pixel source (layer 1, layer 2, screen background or video) has the highest priority. Layer 2 Layer 1 Background Color Video UEA11172 Figure 10-3 Priority of Layers in Overlapped Layer Mode The transparency between layers is supported. Below layer 2 there is layer 1, below layer 1 there is the screen background colour and below screen background there is video. In overlapped layer mode a transparency hierarchy is defined for layer 2, layer 1, screen background and video. The transparency hierarchy is controlled, for each pixel, by two bits (TR1 ... 0) which are defined in the pixel format of the framebuffer and bit SBTL which is defined in instruction SAR. Thus each pixel position can be defined individually as layer 1, layer 2, screen background, video or contrast reduced video. Depending on the transparency bits of both layers, subsequent signals are switched to the RGB, COR and BLANK (normal polarity assumed) outputs of M2. As a result one of the two layers or the screen background will be visible on the screen. If layer 2 is not available for a pixel, signals COR, BLANK and RGB output depends on layer 1 only. Users Manual 10 - 6 2000-06-15 SDA 6000 Display Generator Table 10-1 Layer 1 TR1 0 0 1 1 X*2) X 0 0 1 1 0 0 1 1 X X 0 0 TR0 0 1 0 1 X X 0 1 0 1 0 1 0 1 X X 0 1 Behavior of M2's Outputs in Overlapped Layer Mode Layer 2 TR1 n.a. n.a. n.a. n.a. 0 0 1 1 1 1 n.a. n.a. n.a. n.a. 0 0 1 1 *1) Screen BLANK Background Pin SBTL 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Meshed 0 0 0 Meshed 0 Meshed 0 0 0 Meshed 1 1 0 Meshed 0 Meshed COR Pin 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 RGB Pins Layer 1 Layer 1 Background Background Layer 2 Layer 2 Layer 1 Layer 1 Background Background Layer 1 Layer 1 Background Background Layer 2 Layer 2 Layer 1 Layer 1 RGB Tube Layer 1 Layer 1/ Video Background Background Layer 2 Layer 2/ Video Layer 1 Layer 1/ Video Background Background Layer 1 Layer 1/ Video Video Contrast red. Video Layer 2 Layer 2/ Video Layer 1 Layer 1/ Video TR0 n.a. n.a. n.a. n.a. 0 1 X X X X n.a. n.a. n.a. n.a. 0 1 X X Users Manual 10 - 7 2000-06-15 SDA 6000 Display Generator Table 10-1 Layer 1 TR1 1 1 TR0 0 1 Behavior of M2's Outputs in Overlapped Layer Mode (cont'd) Layer 2 TR1 1 1 TR0 X X Screen BLANK Background Pin SBTL 1 1 1 1 0 1 Background Background Video Contrast red. Video COR Pin RGB Pins RGB Tube *1) *2) n.a. = not available X = don't care For transparency in `screen background area' please refer to Chapter 10.3.3. 10.3.2 Embedded Layers Layer 1 and 2 are not read in parallel to the RAM. The SRU reads only one layer at a time. During the area of layer 2 only pixels of layer 2 are read. Otherwise only layer 1 is read. As a result in the area of layer 2, the pixel information for layer 1 is not available. This is why layer 2 is transparent to video and not to layer 1. As a result, in embedded layer mode, transparency between layers is only supported layer-wise not pixel-wise. Also please refer to transparency using overlapped layers (Chapter 10.3.1). Users Manual 10 - 8 2000-06-15 SDA 6000 Display Generator . Layer 2 Layer 1 Background Color Video UEA11173 Figure 10-4 Priority of Layers in Embedded Layer Mode Depending on the transparency bits of both layers, the following signals are switched to the RGB, COR and BLANK (normal polarity assumed) outputs of M2. As a result, one of the two layers or the screen background will be visible on the screen. If layer 2 is not available for a pixel, signals COR, BLANK and RGB output depends only on layer 1. The transparency hierarchy is again controlled, for each pixel, by two bits (TR1 ... 0) which are defined in the pixel format. On the RGB output of M2 there is a mix of layer 1 and layer 2 RGB stream with the screen background. Depending on the transparency bits of one of the layers subsequent signals are switched to RGB, COR and BLANK (normal polarity assumed). The output signals of M2 (COR, BLANK, RGB) depend only on transparency bits of layer 1 or on layer 2 and never on both layers because there is no pixel position where both layers are available in parallel. 10.3.3 Transparency in Screen Background Area Depending on the height and width definition of layer 1 there is a remaining portion of visible screen area without any pixel definition of layer 1 or layer 2. For this area the transparency bits for layer 1 and layer 2 are not available. For this `Screen Background Area' the colour attributes and transparency attributes are globally defined for the whole screen. Also refer to instruction SAR described in Chapter 10.7.1. Users Manual 10 - 9 2000-06-15 SDA 6000 Display Generator Table 10-2 Layer 1 Behavior of M2's Outputs in Embedded Layer Mode Layer 2 Screen Background SBTL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Meshed 0 0 0 Meshed 0 0 0 Meshed 1 1 0 Meshed 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 Layer 1 Layer 1 Background Background Layer 2 Layer 2 Background Background Layer 1 Layer 1 Background Background Layer 2 Layer 2 Background Background Layer 1 Layer 1 / Video Background Background Layer 2 Layer 2 / Video Background Background Layer 1 Layer 1 / Video Video Contrast red. Video Layer 2 Layer 2 / Video Video Contrast red. Video BLANK Pin COR Pin RGB Pins RGB Tube TR1 0 0 1 1 n.a. n.a. n.a. n.a. 0 0 1 1 n.a. n.a. n.a. n.a. TR0 0 1 0 1 n.a. n.a. n.a. n.a. 0 1 0 1 n.a. n.a. n.a. n.a. TR1 n.a. n.a. n.a. n.a. 0 0 1 1 n.a. n.a. n.a. n.a. 0 0 1 1 TR0 n.a. n.a. n.a. n.a. 0 1 0 1 n.a. n.a. n.a. n.a. 0 1 0 1 Users Manual 10 - 10 2000-06-15 SDA 6000 Display Generator Table 10-3 Behavior of M2's Outputs in Background Area BLANK Pin 0 Meshed 1 1 COR Pin 0 0 0 1 RGB Pins RGB Tube Screen Background STR1 0 0 1 1 STR0 0 1 0 1 RGB values defined in SAR RGB values defined in SAR RGB values defined in SAR RGB values defined in SAR RGB values defined in SAR RGB values defined in SAR/Video Video Contrast red. Video 10.4 Input and Output Formats The transfer of one memory area to another is executed by the graphic accelerator (GA). Transfer means reading data from a source memory area in a given input format, modifying the data and writing it in a defined output format to the destination memory area. Different input and output formats are supported: Table 10-4 1-bit bitmap 2-bit bitmap 4-bit bitmap 8-bit bitmap 8-bit data (for direct data transfer) CLUT1 input 16-bit format (4:4:4:2) Overview on Formats Output Formats 2-bit format CLUT2 vector1) 8-bit format CLUT2 vector 16-bit format (4:4:4:2) RGB 16-bit format (TTX) CLUT2 vector 16-bit format (5:6:5) RGB 8-bit data (for direct data transfer) - Input Formats Note: The 2-bit format is defined as a format for the frame buffer but not supported by the GA. 1) Users Manual 10 - 11 2000-06-15 SDA 6000 Display Generator 10.4.1 Input Formats The following figures describe how bitmaps for different input bit map formats are stored in the source memory area . The 16-bit format is described in Figure 10-12. bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 Byte Address n+1 Memory Addr. = n Memory Addr. = n+2 Pixel 8 Pixel 24 Pixel 9 Pixel 25 Pixel 10 Pixel 26 Pixel 11 Pixel 27 Pixel 12 Pixel 28 Pixel 13 Pixel 29 Pixel 14 Pixel 30 Pixel 15 Pixel 31 Pixel 0 Pixel 16 Pixel 1 Pixel 17 Byte Address n Pixel 2 Pixel 18 Pixel 3 Pixel 19 Pixel 4 Pixel 20 Pixel 5 Pixel 21 Pixel 6 Pixel 22 Pixel 7 Pixel 23 Byte Address n+3 Byte Address n+2 UED11174 Figure 10-5 Format of 1-bitplane Bitmap Note: The 1-bitplane format is used to address vectors 1 ... 0 of CLUT1. bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 Byte Address n+1 Memory Addr. = n Memory Addr. = n+2 Byte Address n Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 4/Bit1 4/Bit0 5/Bit1 5/Bit0 6/Bit1 6/Bit0 7/Bit1 7/Bit0 0/Bit1 0/Bit0 1/Bit1 1/Bit0 2/Bit1 2/Bit0 3/Bit1 3/Bit0 Pixel Pixel Pixel/ Pixel/ Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 12/Bit1 12/Bit0 13/Bit1 13/Bit0 14/Bit1 14/Bit0 15/Bit1 15/Bit0 8/Bit1 8/Bit0 9/Bit1 9/Bit0 10/Bit1 10/Bit0 11/Bit1 11/Bit0 Byte Address n+3 Byte Address n+2 UED11175 Figure 10-6 Format of 2-bitplane Bitmap Note: The 2-bitplane format is used to address vectors 3 ... 0 of CLUT1. bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 Byte Address n+1 Memory Addr. = n Memory Addr. = n+2 Byte Address n Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 2/Bit3 2/Bit2 2/Bit1 2/Bit0 3/Bit3 3/Bit2 3/Bit1 3/Bit0 0/Bit3 0/Bit2 0/Bit1 0/Bit0 1/Bit3 1/Bit2 1/Bit1 1/Bit0 Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 6/Bit3 6/Bit2 6/Bit1 6/Bit0 7/Bit3 7/Bit2 7/Bit1 7/Bit0 4/Bit3 4/Bit2 4/Bit1 4/Bit0 5/Bit3 5/Bit2 5/Bit1 5/Bit0 Byte Address n+3 Byte Address n+2 UED11176 Figure 10-7 Format of 4-bitplane Bitmap Note: The 4-bitplane format is used to address vectors 15 ... 0 of CLUT1. Users Manual 10 - 12 2000-06-15 SDA 6000 Display Generator bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 bit_7 bit_6 bit_5 bit_4 bit_3 bit_2 bit_1 bit_0 Byte Address n+1 Memory Addr. = n Memory Addr. = n+2 Byte Address n Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 1/Bit7 1/Bit6 1/Bit5 1/Bit4 1/Bit3 1/Bit2 1/Bit1 1/Bit0 0/Bit7 0/Bit6 0/Bit5 0/Bit4 0/Bit3 0/Bit2 0/Bit1 0/Bit0 Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel Pixel 3/Bit7 3/Bit6 3/Bit5 3/Bit4 3/Bit3 3/Bit2 3/Bit1 3/Bit0 2/Bit7 2/Bit6 2/Bit5 2/Bit4 2/Bit3 2/Bit2 2/Bit1 2/Bit0 Byte Address n+3 Byte Address n+2 UED11177 Figure 10-8 Format of 8-bitplane Bitmap Note: The 8-bitplane format is used to address vectors 255 ... 0 of CLUT1. 10.4.2 Output Formats The output of the GA is the input of the SRU. The SRU contains a 256 x 14-bit colour look up table (CLUT2). This CLUT2 contains 256 different RGB values with 4 bits for each colour (4:4:4) and 2-bit transparency information. 2-bit formats, 8-bit formats and the TTX format are using this CLUT2. For 16-bit formats (TTX or 4:4:4:2) it depends on bit `M' (mode), if the 16-bit information is used as colour look up vectors or the 16-bit information is bypassing CLUT2. The 5:6:5 format always bypasses CLUT2. DG GA SRU FIFO CLUT2 (256 x 14) RGB Display Generator Interface (DGI) Memory UED11178 Figure 10-9 Overview on SRU Users Manual 10 - 13 2000-06-15 SDA 6000 Display Generator The different formats of pixels stored in a frame buffer which are used by the SRU are described in the following paragraphs: Frame Buffer in 2-bit Pixel Format Using this format, the frame buffer contains colour vectors. These 2-bitplane colour vectors will be converted into 4:4:4:2 format (R:G:B: transparency value) by addressing vector 252 ... 255 of CLUT2. 1 0 1 0 1 0 1 0 Pixel0 7 6 Pixel1 Pixel2 5 4 3 2 Pixel3 1 0 UED11179 Figure 10-10 2-bit Pixel Format for Use in Frame Buffer Frame Buffer in 8-bit Pixel Format Using this format, the frame buffer contains colour vectors. These 8-bitplane colour vectors will be converted into 4:4:4:2 format (R:G:B: transparency value) by CLUT2. Pixel (7...0) 7 6 5 4 3 2 1 0 UED11180 Figure 10-11 8-bit Pixel Format for Use in Frame Buffer Frame Buffer in 16-bit Pixel Format (4:4:4:2 or TTX) This 16-bit format supports an RGB mode (4:4:4:2) and a TTX mode. Which of these modes is in use can be decided pixel by pixel with bit `M': * TTX format (M = `0') * 12-bitplanes RGB (4:4:4:2) format (M = `1') with 2 transparency bits TR(1 ... 0). Note: The meaning of transparency bits is described in more detail in Chapter 10.3.1 and Chapter 10.3.2. Users Manual 10 - 14 2000-06-15 SDA 6000 Display Generator M TR(1..0) Pixel(12..0) 1 Hz Flash 16-Bit TTX Format 2 Hz Flash, Phase 1 0 2 Hz Flash, Phase 2 2 Hz Flash, Phase 3 1 1 0 0 1 0 1 0 C 2) (2..0) FlashC(4..0) 3) Pixel(4..0) 4) Transparency Level 1 16-Bit 4:4:4:2 Format Transparency Level 2 1 Transparency Level 3 Transparency Level 4 0 0 1 1 0 1 0 1 I1) Red(3..0) 5) Green(3..0) 5) Blue(3..0) 5) 1) 2) 3) 4) 5) I - Italic Subpixel C - CLUT2 Selector in TTX mode FlashC - CLUT2 Vector for Flash Colour in TTX mode Pixel - CLUT2 Vector for Pixel in TTX mode Red Green Blue - Pixel RGB Colour in 4:4:4:2 mode UED11181 Figure 10-12 16-bit Pixel Format (4:4:4:2/TTX) for Use in Frame Buffer Pixels in 16-bit format which are stored in TTX format contain two 5-bit colour look up vectors and two flash mode indicator bits. The flash mode indicator bits are used to choose the flash rate and the flash phase. The meaning of flash is: The colour alternates between two 5-bit colour vectors (FlashC and Pixel) which are chosen within the format definition. * Non Flash: Flash can be disabled if both 5-bit colour vectors point to the same CLUT2 location. * Inverted Flash: Inverted flash is supported by exchanging the `FlashC' vector with the `Pixel' vector. Users Manual 10 - 15 2000-06-15 SDA 6000 Display Generator Slow Rate Flash. Normal Flash Fast Rate Flash. Phase 1. Normal Flash Fast Rate Flash. Phase 2. Normal Flash Fast Rate Flash. Phase 3. Normal Flash UED11182 Figure 10-13 Internally Generated Flash Signals in Different Flash Phases 5-bit colour look up vectors are converted into a 12-bit RGB value and a 2-bit transparency level by CLUT2 during display. To do this, the input side of CLUT2 the 5bit look up value is used for Bit0 to Bit4, the C2-values are used as Bit7 to Bit5. The 12bit RGB value is fed to the D/A converter and the 2-bit transparency information to the BLANK/COR pins. 16-bit format pixels which are stored in the 12-bit RGB format are not passing the CLUT2. The 12-bit RGB value and the 2-bit transparency information is directly fed into the D/A converter and the BLANK/COR pins. Frame Buffer in 16-bit Pixel Format (5:6:5) In this mode the frame buffer contains RGB values with 5 bits for red colour components, 6 bits for green colour components and 5 bits for blue colour components: 4 3 2 Red 1 0 5 4 Green 3 2 1 Green 0 4 3 2 Blue 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UED11183 Figure 10-14 16-bit Pixel Format (5:6:5) for Use in Frame Buffer Transparency between layers is not supported if this mode is in use. The 5:6:5 format is directly transferred to the D/A converter. CLUT2 is out of use in this mode. Users Manual 10 - 16 2000-06-15 SDA 6000 Display Generator 10.5 Initialization of Memory Transfers Transferring an input format of the source area to an output format in the destination area is supported by different transfer modes. For this, a pixel modification unit and CLUT1 of the GA is used. CLUT1 has a size of 256 x 16 bit. Next to the transfer mode the transfer areas (source and destination) must be defined by GA instructions. Source is either an address in the external memory or a constant value coming from CLUT1. Destination is always an address in the external memory. Constant values coming from CLUT1 are used to draw lines or fill parallelograms. DG GA Pixel Modification CLUT1 (256 x 16) SRU Display Generator Interface (DGI) Memory UED11184 Figure 10-15 Overview of GA 10.5.1 Transfer Modes Different transfer modes are available. The table below shows all possible combinations of input and output formats. `Transparency available' means that if transparency mode is chosen (see also GAIinstruction `TAR' (Bit: TRM)) and Bit TR1 of the output word is set to `0' (refer also to Figure 10-12) this pixel is written to the destination, otherwise this pixel is not written to the destination. `Modification' describes in which way the output information is generated by using the input information, CLUT1 and the settings of the `TAR'-instruction. Using 16-bit TTX output two bits are replaced by another 2 bits (Flash) which are also defined by graphic accelerator instruction `TAR'. The table below shows all possible combinations of input and output formats: Users Manual 10 - 17 2000-06-15 SDA 6000 Display Generator Table 10-5 Supported Transfer Modes Transparency Available No Modification OUT(15) = `0' OUT(14 ... 13) = FLA(1 ... 0) OUT(12 ... 0) = CLUT1(`0000000' & IN(0))(12 ... 0) OUT(15) = `1' OUT(14 ... 13) = CLUT1(`0000000' & IN(0))(14 ... 13)) OUT(12) = IT OUT(11 ... 0) = CLUT1(`0000000' & IN(0))(11 ... 0)) OUT(7 ... 0) = CLUT1(`0000000' & IN(0))(7 ... 0) OUT(15 ... 0) = CLUT1(`0000000' & IN(1 ... 0))(15 ... 0)) OUT(15) = `0' OUT(14 ... 13) = FLA(1 ... 0) OUT(12 ... 0) = CLUT1(`000000' & IN(1 ... 0))(12 ... 0) OUT(15) = `1' OUT(14 ... 13) = CLUT1(`0000000' & IN(1 ... 0))(14 ... 13)) OUT(12) = IT OUT(11 ... 0) = CLUT1(`0000000' & IN(1 ... 0))(11 ... 0)) OUT(7 ... 0) = CLUT1(`000000' & IN(1 ... 0))(7 ... 0) OUT(15 ... 0) = CLUT1(`000000' & IN(1 ... 0))(15 ... 0)) OUT(15) = `0' OUT(14 ... 13) = FLA(1 ... 0) OUT(12 ... 0) = CLUT1(`0000' & IN(3 ... 0))(12 ... 0) TMOD Input Output (4 ... 0) Format Format 00000 1-bit bitmap 16-bit (TTX) 00001 1-bit bitmap 16-bit (4:4:4:2) Yes 00010 00011 00100 1-bit bitmap 1-bit bitmap 2-bit bitmap 8-bit 16-bit (5:6:5) 16-bit (TTX) No No No 00101 2-bit bitmap 16-bit (4:4:4:2) Yes 00110 00111 01000 2-bit bitmap 2-bit bitmap 4-bit bitmap 8-bit 16-bit (5:6:5) 16-bit (TTX) No No No Users Manual 10 - 18 2000-06-15 SDA 6000 Display Generator Table 10-5 Supported Transfer Modes (cont'd) Transparency Available Yes Modification OUT(15) = `1' OUT(14 ... 13) = CLUT1(`0000000' & IN(3 ... 0))(14 ... 13)) OUT(12) = IT OUT(11 ... 0) = CLUT1(`0000000' & IN(3 ... 0))(11 ... 0)) OUT(7 ... 0) = CLUT1(`0000' & IN(3 ... 0))(7 ... 0) OUT(15 ... 0) = CLUT1(`0000' & IN(3 ... 0))(15 ... 0)) OUT(15) = `0' OUT(14 ... 13) = FLA(1 ... 0) OUT(12 ... 0) = CLUT1(IN(7 ... 0))(12 ... 0) OUT(15) = `1' OUT(14 ... 13) = CLUT1(`0000000' & IN(7 ... 0))(14 ... 13)) OUT(12) = IT OUT(11 ... 0) = CLUT1(`0000000' & IN(7 ... 0))(11 ... 0)) OUT(7 ... 0) = CLUT1(IN(7 ... 0))(7 ... 0) OUT(15 ... 0) = CLUT1(IN(7 ... 0))(15 ... 0)) OUT(7 ... 0) = CLUT1(0)(7 ... 0) OUT(15) = `0' OUT(14 ... 13) = FLA(1 ... 0) OUT(12 ... 0) = CLUT1(0)(12 ... 0) OUT(15) = `1' OUT(14 ... 0) = CLUT1(0)(14 ... 0)) OUT(15 ... 0) = IN(15 ... 0) TMOD Input Output (4 ... 0) Format Format 01001 4-bit bitmap 16-bit (4:4:4:2) 01010 01011 01100 4-bit bitmap 4-bit bitmap 8-bit bitmap 8-bit 16-bit (5:6:5) 16-bit (TTX) No No No 01101 8-bit bitmap 16-bit (4:4:4:2) Yes 01110 01111 10000 10001 8-bit bitmap 8-bit bitmap CLUT1 input CLUT1 input CLUT1 input 8-bit 16-bit (5:6:5) 8-bit 16-bit (TTX) 16-bit (4:4:4:2) No No No No 10010 10011 Yes Only In 4:4:4:2 Mode 16-bit 16-bit (TTX or (TTX or 4:4:4:2) 4:4:4:2) Users Manual 10 - 19 2000-06-15 SDA 6000 Display Generator Table 10-5 Supported Transfer Modes (cont'd) Transparency Available Modification OUT(7 ... 0) = IN(7 ... 0) TMOD Input Output (4 ... 0) Format Format 10100 Others 8-bit data Reserved 8-bit data No Note: There is no transfer mode defined which uses the 2-bit format as an output format, because in this case layer 2 is restricted to a width of 64 pixels. If the 2-bit format is required, the direct byte by byte transfer can be used. 10.5.2 Transfer Areas Next to the transfer mode the transfer area has to be defined by graphic accelerator instructions (GAI). For source and destination, `linear' and `rectangle' areas can be defined. `Linear' means that data is accessed byte by byte without any irregularity in the addressing of the memory. `Rectangle' means that after the access of n bytes defined by a parameter `width' an `offset' to the last address is automatically added. This feature can be used if an array of data has to be copied from one memory location into another (bigger) array at any other memory location. The linear addressing is a subset of the rectangle addressing scheme if `offset' is set to `0'. Source Area There are different settings necessary to define the source area. These settings are done by using the graphic accelerator instruction set. The table below describes the necessary settings and corresponding GAIs with the affected bit position inside the GAI: Used GAI SDR TSR TOR Bit Position Inside GAI S_ADDR WIDTH_IN S_OFFSET Description Start address of source area Width of source area Offset to describe rectangular source areas Users Manual 10 - 20 2000-06-15 SDA 6000 Display Generator As described before, there are seven different formats on the input side of the transfer: * * * * * * * 1-bit bitmap 2-bit bitmap 4-bit bitmap 8-bit bitmap 8-bit data (used for direct data transfer) CLUT1 input (used for drawing of filled parallelograms, rectangles, lines) 16-bit (4:4:4:2) RGB CLUT1 input does not need any more detailed area description. The input value comes directly from the address `0' of CLUT1 and not from the RAM. This mode can be used for drawing lines, filling rectangles or parallelograms. For the other input modes a more detailed description is given below: From the point of view of the register settings, which are used to define the source area, the different input formats can be divided in three groups which are handled in different ways. Group 1: 1-bit bitmap 2-bit bitmap 4-bit bitmap Group 2: 8-bit data 8-bit bitmap Group3: 16-bit pixel format (4:4:4:2) Formats of group 1 are formats which define each pixel with less than a byte. Group 2 formats are formats which define each pixel by 8 bits, and group 3 formats are formats which define each pixel by 16 bits. Group 1: In 1-bit bitmap, 2-bit bitmap and 4-bit bitmap input mode it is expected, that the bitmaps are stored linearly in the memory as described in Chapter 10.4.1. Therefore the settings of WIDTH_IN as well as S_OFFSET are ignored. Only the 24-bit source address pointer S_ADDR is used. The amount of pixels which are read from the source and written to the destination is only defined by the destination settings. The user has to take care that the destination settings fit with the bitmap inherent alignments. Group 2: In this mode WIDTH_IN and S_OFFSET are also taken into account. The amount of memory which is described by WIDTH_IN and S_OFFSET is described by numbers of bytes. Group 3: In this mode WIDTH_IN and S_OFFSET are also taken into account. The amount of memory which is described by WIDTH_IN and S_OFFSET is described by numbers of words. Note: The number of bytes to be read from the source area is defined by the destination area (see below) and the transfer mode. This is why no explicit definition of height is needed for the source. Users Manual 10 - 21 2000-06-15 SDA 6000 Display Generator MEMORY S_ADDR WIDTH_IN (TSR) S_OFFSET (TOR) Source Area UED11185 Figure 10-16 Use of Register Settings to Specify Source Area Destination Area There are additional settings necessary to define the destination area. The table below describes the settings and the corresponding GAIs with the affected bit position inside the GAI: Used GAI DDR TDR TOR Bit Position Inside GAI D_ADDR HEIGHT_OUT, WIDTH_OUT D_OFFSET Description Start address of destination area Height and width of destination area Offset to describe rectangular destination areas Next to the destination area itself a clipping area can be defined. The clipping area needs to be defined within the destination area. During a memory transfer these `clipped' memory areas are excluded from the transfer. The table below describes the settings and the corresponding GAIs with the affected bit positions inside the GAI: Used GAI CUR CBR CBR, CUR Bit Position Inside GAI C_ADDR HEIGHT_CLIP, WIDTH_CLIP C_OFFSET Description Start address of clipping area Height and width of clipping area Offset to describe rectangular clipping areas 10 - 22 2000-06-15 Users Manual SDA 6000 Display Generator As described before, there are five different formats on the output side of the transfer: (Also please refer to Chapter 10.4.2) * * * * * 8-bit format CLUT2 vector 16-bit format (4:4:4:2) RGB 16-bit format (TTX) CLUT2 vector 16-bit format (5:6:5) RGB Direct data transfer (byte by byte) From the point of view of the register settings which are used to define the alignment of the destination area, these formats can be divided in two groups. Each group is handled in a different way. Group 1: 16-bit format (4:4:4:2) RGB 16-bit format (TTX) CLUT2 vector 16-bit format (5:6:5) RGB Group 2: 8-bit format CLUT2 vector 8-bit data (byte by byte transfer) Formats of group 1 are formats which define each pixel by 16 bits. Group 2 formats are formats which define each pixel by 8 bits. Note: Bit fields HEIGHT_CLIP, HEIGHT_OUT and WIDTH_CLIP, WIDTH_OUT describe the height and width of the destination in count of pixels and not in bytes. So for output formats of group 1 the memory area which is described by a HEIGHT_OUT value and a WIDTH_OUT value needs the double amount of memory, than output formats which are described by the same HEIGHT_OUT value and WIDTH_OUT value for output formats of group 2. Also, the OFFSET values are pixels and not bytes or words. C_ADDR and D_ADDR are real byte addresses in memory. Note: For a rectangle destination area the sum of WIDTH and D_OFFSET of the destination area must be equal to the width of the frame buffer (WIDTH_L1(2)). Otherwise the shape of the copied frame will be a parallelogram and not a rectangle. Note: For a rectangle clipping area inside the destination area the sum of the clipping offset and the clipping width must be the same as the sum of the destination area width and the destination offset. Otherwise the clipping area will be a parallelogram and not a rectangle. Note: Source area and destination area should not overlap. Otherwise it may appear that a pixel is overwritten as a destination pixel, and afterwards used as a source pixel. Users Manual 10 - 23 2000-06-15 SDA 6000 Display Generator Meaning of Double Width and Double Height during Transfer The destination area can be stretched horizontally and vertically by using GA instruction TAR. If double width (TDW) is set to `1', the graphic accelerator writes each pixel twice horizontally to the destination area. TQH 0 0 TDH 0 1 Meaning Normal transfer If double height (TDH) is set to `1' and quadruple height (TQH) is set to `0' in the destination output side each pixel in vertical direction is repeated twice. If quadruple height (TQH) is set to `1' on the destination output side each pixel in vertical direction is repeated four times. 1 X If double height (TDH) is set to `1' in the destination output side each pixel in vertical direction is repeated twice. For example: If double width is set to `1' and quadruple height is set to `1' each pixel of the source area needs 8 pixels of the destination area. Note: Parameters like WIDTH_OUT, WIDTH_CLIP, HEIGHT_OUT and HEIGHT_CLIP are still pixel related. WIDTH_OUT, HEIGHT_OUT and D_OFFSET have to be adapted by the software to get a complete character. Clipping is not affected by TDH and TDW. The following table is an example of a 1-bit bitmap (30 x 50) which should be transferred either in normal size or in double size to an 8 bit output format in a frame buffer with a size of 100 x 200 pixels. Parameters WIDTH_L1 HEIGHT_L1 WIDTH_IN WIDTH_OUT D_OFFSET HEIGHT_OUT 30 70 50 TDW = 0; TDH = 0; TQH = 0 TDW = 1; TDH = 1; TQH = 0 100 200 30 60 40 100 Note: In case of double width transfer WIDTH_OUT has to be an even number. In case of double/quad height transfer HEIGHT_OUT has to be an even/divisable by 4 number. Users Manual 10 - 24 2000-06-15 SDA 6000 Display Generator Figure 10-17 gives a graphical overview of how to specify the different areas. Frame Buffer FB_ADDR WIDTH_L1(2) (FSR) D_ADDR C_ADDR Destination Area HEIGHT_OUT (TDR) HEIGHT_CLIP (CBR) Clipping Area HEIGHT_L1(2) (FSR) WIDTH_OUT (TDR) D_OFFSET (TOR) C_OFFSET (CUR, CBR) WIDTH_CLIP (CBR) C_OFFSET (CUR, CBR) UED11186 Figure 10-17 Use of Register Settings to Specify Destination and Clipping Area 10.5.3 Italic Mode For transfer modes with 16-bit (4:4:4:2) format as an output, an automatic italic transfer option is available. If italic mode is chosen only the destination area (not the source area) is affected. The following two figures explain the different representation of pixels in the frame buffer in non-italic and italic mode. D_ADDR D_OFFSET WIDTH_OUT D_OFFSET Bit 'I' of 4:4:4:2 format HEIGHT_OUT 0 0 0 0 0 0 0 0 0 0 UED11187 Figure 10-18 Result for a Non-italic Transferred Memory Area in Frame Buffer Users Manual 10 - 25 2000-06-15 SDA 6000 Display Generator If this transfer is executed with the same register settings but in italic mode instead of non italic mode, the subsequent destination area is used inside the frame buffer: D_ADDR D_OFFSET WIDTH_OUT D_OFFSET Bit 'I' of 4:4:4:2 format HEIGHT_OUT 1 0 1 0 1 0 1 0 1 0 UED11188 Figure 10-19 Result for a Italic Transferred Memory Area in Frame Buffer Next to the destination pixel offset from line to line, the italic bit (`I') alternates from line to line. This italic bit is used to control the D/A converter to realize a horizontal line alternating half pixel shift on RGB output. UED11189 Figure 10-20 Result for an Italic Transferred Memory Area at D/A Converter Output Note: Italic can not be used together with double width and double/quad height transfers. Users Manual 10 - 26 2000-06-15 SDA 6000 Display Generator 10.6 10.6.1 Register Description Special Function Registers The display generator is controlled by 3 special function registers and a list of accelerator instructions. Two of the registers define the position and the length of the instruction list, and one register is used for general control of the DG. After the list of instructions (GAIs) is written to the memory, the start address and the length of this list must be written to special function registers GPRGCRH and GPRGCRL. Then the controller commands the GA to execute these instructions (see SFR DGCON). After the GA has finished executing all GAIs, the GA gives the controller an interrupt (GAFIR). Note: GPRGCRH, GPRGCRL and DGCON are the only special function registers to control the display generator. GAIs described in the next paragraph are stored in the RAM and not defined after power on. GPRGCRH 15 14 13 12 11 GCR (8..0) Reset Value: 0000H 10 9 8 7 6 5 4 3 2 1 0 GPR (23..17) rw rw Bit GCR (8 ... 0) Function Defines the amount of GAIs in the instruction list. GCR x 4 is the length of the GAI area in count of bytes. Note: After the last instruction is executed an interrupt is given to the controller GPR Define the MSBs of the 23-bit address pointer to the start of the GAI (23 ... 17) area. GPRGCRL 15 14 13 Reset Value: 0000H 3 2 1 0 12 11 10 9 8 7 6 5 4 GPR (16..1) rw Bit Function GPR Define the LSBs of the 23-bit address pointer to the start of the GAI (16 ... 1) area. DGCON is for general control of the DG. Users Manual 10 - 27 2000-06-15 SDA 6000 Display Generator DGCON 15 - Reset Value: 0000H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 BSY GA 2 ST GA 1 EO DG 0 EA DG r rw rw rw Bit EADG Function Enables access from DG to SDRAM. 0: All requests from DG (SRU and GA) to the memory are disabled. 1: The DG has normal access to the memory. Note: The running memory access is finalized before this bit becomes active. EODG Enables output of DG. 0: All outputs of the DG are disabled (RGB outputs are switched to black level, COR = 0 and BLANK = 1) (`Normal' pin polarity assumed. Please refer also to register SCR). 1: The outputs have the function according to the specifications described in the following paragraphs. Note: The SRU registers FBR and DBR have to be programmed with a valid memory address before enabling display output. STGA Starts processing of the instruction list by the GA 0: STGA has to be reset by SW before the GA can be started again. 1: The GA starts the execution of the instruction list at address GPR. It ends after the specified number of instructions (see bit field GCR) is executed. After that an interrupt (GAFIR) is given to the controller. 0: 1: GA is idle, waiting for GAI sequence. GA is busy, GAI sequence is processed. GABSY Users Manual 10 - 28 2000-06-15 SDA 6000 Display Generator The register PXDEL controls an individual delay of 0 ... 2 clock cycles of the SRU outputs. Each output (R, G, B, Italic, blank, cor) is contolled by 2 bits in the PXDEL register. PXDEL 15 res Reset Value: 0000H 13 res 14 res 12 res 11 10 9 8 Tblank 7 6 Titalic 5 Tblu 4 3 2 1 Tred 0 Tcor Tgreen Bits 1...0 3...2 5...4 7...6 9...8 11 ... 10 15 ... 12 Bits set to delay for red delay for green delay for blue delay for italic delay for blank delay for cor reserved "00" "01" "10" "11" - no delay - delay of 1 pixel clock cycle - delay of 2 pixel clock cycles - reserved The reset value of PXDEL is set to 0000H, which means no dely of the SRU outputs after reset. Users Manual 10 - 29 2000-06-15 SDA 6000 Display Generator 10.7 Description of Graphic Accelerator Instructions GAIs are 32-bit instructions which are used as an interface from C to DG. They are written sequentially to the SDRAM by the controller in form of an instruction list. Figure 10-21 shows the organization of GAIs in the memory. Byte Address n+3+k x 4 Byte Address n+2+k x 4 Byte Address n+1+k x 4 Byte Address n+k x 4 GAI-No. k Byte Address n+7 Byte Address n+6 Byte Address n+5 Byte Address n+4 Byte Address n+3 Byte Address n+2 Byte Address n+1 Byte Address n GAI-No. 0 GAI-No. 1 Standard Format for GAIs: 31 30 29 28 27 26 25 24 23 22 GAI_BYTE 1 GAI_BYTE 3 15 14 13 12 11 10 9 8 7 6 5 21 20 19 18 17 16 GAI_BYTE 0 GAI_BYTE 2 4 3 2 1 0 UED11190 Figure 10-21 Organization of GAIs in the External SDRAM Users Manual 10 - 30 2000-06-15 GAI-No. ... SDA 6000 Display Generator In the following GAI description, `-' means that these bits are reserved for future use and have to be set to `0'. The meaning of an instruction is not given by the physical location (address) of the instruction but by its opcode which is represented by bits 31 ... 28. Bits 27 ... 0 are equivalent to an operand. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Opcode Operand(s) Operand(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 10-22 GAI Instruction Format There are two types of GAIs. One type is used to setup global parameters for SRU and GA, like SRU setup, frame buffer setup or CLUT setup. The second type of GAI is used to setup the transfer parameters for DMA functions. Global Parameters The following global instructions are only executed by the GA during the vertical sync area. If such a GA-instruction is read by the GA outside the V-sync area, it waits until the next V-sync appears. Note: The V-sync area is defined for that purpose as the first 4 lines of a field. * SRU setup SAR (opcode = 1111) - set screen attributes * Frame buffer 1 (layer 1) and frame buffer 2 (layer 2) setup FBR (opcode = 1000) - set address of the beginning of frame buffer 1 FSR (opcode = 1001) - set size of frame buffer 1 DBR (opcode = 1010) - set address of the beginning of frame buffer 2 DSR (opcode = 1011) - set size of frame buffer 2 DCR (opcode = 1100) - set frame buffer 2 reference coordinates * CLUT Setup CLR (opcode = 1101) - set contents of the CLUT1 or CLUT2 Note: If CLUT2 should be loaded the GA waits until the next V-sync appears. * No operation NOP (opcode = 1110) - no operation Users Manual 10 - 31 2000-06-15 SDA 6000 Display Generator Transfer Parameters These instructions are immediately executed by the GA. * * * * * * * * CUR (opcode = 0000) - set clipping coordinates CBR (opcode = 0001) - set clipping coordinates SDR (opcode = 0010) - set source descriptor for data transfer DDR (opcode = 0011) - set destination descriptor for data transfer TSR (opcode = 0100) - set definitions for source memory area TDR (opcode = 0101) - set definitions for destination memory area TOR (opcode = 0110) - set offset definitions for transferred area TAR (opcode = 0111) - set attributes for transfer 10.7.1 SAR 31 1 Screen Attributes (SAR) This instruction controls different screen attributes. 30 1 29 1 28 1 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 SB TL 19 18 17 16 DMODE(3..0) DDW DDH STR(1..0) RED(3..0) GREEN(3..0) BLUE(3..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit SBTL Function Screen Background Transparency under Layer Area Defines whether the screen background area is transparent under a layer 1 (2) area or not. 0: The screen background within a layer area is not transparent. Under transparent layer pixels the background colour can be seen. 1: The screen background within a layer area is transparent. Under transparent layer pixels the video can be seen. Note: Transparency definitions for the screen background outside a layer area are made with bits STR. Also please refer to Chapter 10.3.3. DMODE (3 ... 0) Display Mode Bits Defines the possible combinations of both layers with the available pixel formats. Please see table `Display Modes' below. Users Manual 10 - 32 2000-06-15 SDA 6000 Display Generator Bit DDW Function Double Width Display 0: Normal width 1: Double width. The contents of the screen are stretched in horizontal direction. The SRU repeats the same pixel information twice in horizontal direction. Note: DDW = `1' the frame buffer width (WIDTH_L1(L2) has to be divided by two to get the same area displayed on the screen. DDH Double Height Display 0: Normal height 1: Double height. The contents of the screen are stretched in vertical direction. The SRU repeats the same pixel information twice in vertical direction. Note: DDH = `1' the frame buffer height (HEIGHT_L1(L2) has to be divided by two to get the same area displayed on the screen. STR (1 ... 0) RED (3 ... 0) GREEN (3 ... 0) BLUE (3 ... 0) Screen Background Transparency Level Define the transparency of the screen background area outside the layer area. Please refer to Chapter 10.3.3. Screen Background Red Colour 4-bit red component Screen Background Green Colour 4-bit green component Screen Background Blue Colour 4-bit blue component Users Manual 10 - 33 2000-06-15 SDA 6000 Display Generator Table 10-6 DMODE (3 ... 0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Display Modes Layer Formats Layer 1 16-bit (4:4:4:2 or TTX) 8-bit 16-bit (5:6:5) - reserved reserved 16-bit (4:4:4:2 or TTX) reserved 16-bit (4:4:4:2 or TTX) 8-bit 16-bit (4:4:4:2 or TTX) 8-bit 16-bit (5:6:5) reserved 16-bit (4:4:4:2 or TTX) 8-bit 8-bit 16-bit (4:4:4:2 or TTX) 16-bit (5:6:5) embedded embedded embedded embedded embedded 2-bit overlapped Layer 2 - - - - - Layer 2 switched off Layer 2 switched off Layer 2 switched off Layer 1 & 2 switched off - Layer Mode Users Manual 10 - 34 2000-06-15 SDA 6000 Display Generator 10.7.2 FBR 31 1 Startaddress of Layer 1 (FBR) The start address of frame buffer 1 in the memory must be set by the controller. 30 0 29 0 28 0 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 FB_ADDR(23..16) FB_ADDR(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit FB_ADDR (23 ... 0) Function Startaddress of frame buffer 1 Bit 23 ... 0 of a byte address. 10.7.3 FSR 31 1 Size of Layer 1 (FSR) 30 0 29 0 28 1 27 - 26 - 25 24 23 22 21 20 19 18 17 16 HEIGHT_L1(9..0) - - - - - WIDTH_L1(10..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit HEIGHT_L1 (9 ... 0) WIDTH_L1 (10 ... 0) Function Height of Frame Buffer 1 The height of the frame buffer can vary between 0 (HEIGHT_L1 = `0'd) and 1023 pixels (HEIGHT_L1 = `1023'd). Width of Frame Buffer 1 The width of the frame buffer can vary between 0 (WIDTH_L1 = `0'd) and 2046 pixels (WIDTH_L1 = `2046'd). Users Manual 10 - 35 2000-06-15 SDA 6000 Display Generator 10.7.4 DBR 31 1 Startaddress of Layer 2 (DBR) The start address of frame buffer 2 in the memory must be set by the controller. 30 0 29 1 28 0 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 DB_ADDR(23..16) DB_ADDR(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit DB_ADDR (23 ... 0) Function Startaddress of Frame Buffer 2 Bit 23 ... 0 of a byte address. 10.7.5 DSR 31 1 Size of Layer 2 (DSR) 30 0 29 1 28 1 27 - 26 - 25 24 23 22 21 20 19 18 17 16 HEIGHT_L2 - - - - - WIDTH_L2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit HEIGHT_L2 (9 ... 0) WIDTH_L2 (10 ... 0) Function Height of Layer 2 The height of layer 2 can vary between 0 (HEIGHT_L2 = `0'd) and 1023 pixels (HEIGHT_L2 = `1023'd). Width of Layer 2 The width of the layer 2 can vary between 0 (WIDTH_L2 = `0'd) and 2046 pixels (WIDTH_L2 = `2046'd). Note: Width_L2 is ignored, if layer 2 is displayed in 2-bit CLUT2 vector format. In this case width_L2 is set to 64. Users Manual 10 - 36 2000-06-15 SDA 6000 Display Generator 10.7.6 Display Coordinates of Layer 2 (DCR) This instruction is used to place layer 2 in layer 1. By these coordinates the left top corner of layer 2 is placed in relation to the top left corner of layer 1. In this sense the coordinate ULY = 0/ULX = 0 is identical to the top left corner of layer 1. Negative coordinates are also supported so it is also possible to move a layer 2 window from the top or left side of a layer 1 window. DCR 31 1 30 1 29 0 28 0 27 - 26 25 24 23 22 21 ULY(10..0) 20 19 18 17 16 - - - - ULX(11..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit ULY (10 ... 0) Function Upper left corner Y-coordinate in one's complement representation: `11111111111' = `- 1023D' ... `10000000000' = `- 0D' `00000000000' = `+ 0D' ... `01111111111' = `+ 1023D' ULX (11 ... 0) Upper left corner X-coordinate in one's complement representation: `111111111111' = `- 2046D' ... `100000000000' = `- 0D' `000000000000' = `+ 0D' ... `011111111111' = `+ 2046D' Users Manual 10 - 37 2000-06-15 SDA 6000 Display Generator 10.7.7 CLR 31 1 Contents of CLUT (CLR) CLR instruction allows the contents of the CLUT1 and CLUT2 to be set. 30 1 29 0 28 1 27 - 26 - 25 - 24 23 22 21 20 19 18 17 16 CLUT_ADDR(8..0) CLUT_CONTENT(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit CLUT_ ADDR (8 ... 0) Function CLUT address Bits 7 ... 0 are CLUT vectors of either CLUT1 or CLUT2. Bit 8 selects the CLUT: 0: CLUT1 (256 x 16 bit) 1: CLUT2 (256 x 14 bit) Contents to be written to one of the look up tables addressed by the CLUT vector defined above. For CLUT1 all the 16 bits are used, for CLUT2 only bits 13 ... 0 are used. CLUT_ CONTENT (15 ... 0) 10.7.8 Clipping Coordinates (CUR and CBR) These GAIs are used to set clipping coordinates for memory transfers. The clipping coordinates describe a rectangle area in the destination memory area. During a memory transfer these `clipped' memory areas are excluded from the transfer. The CUR instruction is used to set the clipping start address. The CBR instruction is used to set the width and height of the clipping area in amounts of pixels. A width of `0' means that no clipping is processed, a width of `1' means the clipping area has the width of 1 pixel, .... A height of `0' means, that no clipping is processed, a height of `1' means the clipping area has the height of 1 line, ... . Next to the start address, height and width a clipping offset must be given for clipping. For a rectangle clipping area the sum of this clipping offset and the clipping width must be the same as the sum of the destination area width and the destination offset. Otherwise the clipping area will be a parallelogram, not a rectangle. Within instruction TAR it is decided whether the clipping area is inverted or non inverted. Thus the outside region of the defined rectangle can be used for clipping as well as the inside region. Please also refer to Chapter 10.5.2. Users Manual 10 - 38 2000-06-15 SDA 6000 Display Generator CUR 31 0 30 0 29 0 28 0 27 26 25 24 23 22 21 20 19 18 17 16 C_OFFSET(3..0) CLIPPING_ADDR(23..16) CLIPPING_ADDR(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit C_OFFSET (3 ... 0) CLIPPING _ADDR (23 ... 0) CBR 31 0 Function Clipping Offset (Bit3 ... 0) The MSBs of C_OFFSET are defined by instruction CBR Beginning of the clipping area Bit 23 ... 0 of a byte address. 30 0 29 0 28 1 27 26 25 24 23 22 21 20 19 18 17 16 HEIGHT_CLIP(9..0) C_OFFSET (10..9) C_OFFSET(8..4) WIDTH_CLIP(10..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit HEIGHT_ CLIP (9 ... 0) C_OFFSET (10 ... 4) WIDTH_ CLIP (10 ... 0) Function Height of the clipping area The height of the clipping area can vary between 0 (HEIGHT_CLIP = `0d') and 1023 pixels (HEIGHT_CLIP = `1023d'). Clipping Offset (Bit 10 ... 4) The LSBs of C_OFFSET are defined by instruction CUR. Width of the clipping area The width of the clipping area can vary between 0 (WIDTH_CLIP = `0d') and 2046 pixels (WIDTH_CLIP = `2046d'). Users Manual 10 - 39 2000-06-15 SDA 6000 Display Generator 10.7.9 SDR 31 0 Source Descriptor for Data Transfer (SDR) This instruction defines the beginning of the memory area to be read and transferred. 30 0 29 1 28 0 27 GO 26 - 25 - 24 - 23 22 21 20 19 18 17 16 S_ADDR(23..16) S_ADDR(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit GO S_ADDR (23 ... 0) Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Start address of memory area to be transferred. Bit 23 ... 0 of a byte address. This instruction defines the beginning of the destination memory area. DDR 31 0 30 0 29 1 28 1 27 GO 26 - 25 - 24 - 23 22 21 20 19 18 17 16 D_ADDR(23..16) D_ADDR(15..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit GO D_ADDR (23 ... 0) Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Beginning of the destination memory area Bit 23 ... 0 of a byte address. Users Manual 10 - 40 2000-06-15 SDA 6000 Display Generator 10.7.10 Source Size of Transferred Memory Area (TSR) This register contains different information depending on transfer mode. The size of transferred memory is described by width and height of the source of the transfer area. Please also refer to Chapter 10.5.2. TSR 31 0 30 1 29 0 28 0 27 GO 26 - 25 - 24 - 23 22 - 21 - 20 - 19 - 18 - 17 - 16 - - - - - - WIDTH_IN(10..0) 15 Bit GO 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Width of the transferred area in count of pixels. WIDTH_IN = `0': No transfer will be executed. WIDTH_IN (10 ... 0) Users Manual 10 - 41 2000-06-15 SDA 6000 Display Generator 10.7.11 TDR 31 0 Destination Size of Transferred Memory Area (TDR) 30 1 29 0 28 1 27 GO 26 - 25 24 23 22 21 20 19 18 17 16 HEIGHT_OUT(9..0) - - - - - WIDTH_OUT(10..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit GO HEIGHT_ OUT (9 ... 0) WIDTH_ OUT (10 ... 0) Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Height of the transferred area in count of pixels HEIGHT_OUT = `0': No transfer will be executed. Width of the transferred area in count of pixels WIDTH_OUT = `0': No transfer will be executed. Users Manual 10 - 42 2000-06-15 SDA 6000 Display Generator 10.7.12 TOR 31 0 Offset of Transferred Memory Area (TOR) This instruction defines the offset value for rectangle memory transfers. 30 1 29 1 28 0 27 GO 26 25 24 23 22 21 20 19 18 17 16 D_OFFSET(10..0) - - - - - S_OFFSET(10..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit GO S_OFFSET (10 ... 0) D_OFFSET (10 ... 0) Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Source offset value for non linear transfer For more information about S_OFFSET refer to Chapter 10.5.2. Destination offset value for non linear transfer For more information about D_OFFSET refer to Chapter 10.5.2. Users Manual 10 - 43 2000-06-15 SDA 6000 Display Generator 10.7.13 TAR 31 0 Attributes of Transfer (TAR) This instruction defines the transfer mode. 30 1 29 1 28 1 27 GO 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - - TQH UN CL(1..0) TRM TMODE(4..0) IT TDW TDH FLA(1..0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 10-7 Bit GO TQH Function Must be set to `1' if GA is to start memory transfer after executing this GA-instruction. Otherwise this bit must be set to `0'. Quadruple Height during Transfer `0': Normal height is selected. `1' The memory transfer is stretched in vertical direction on the output side. Underline on/off 0: Underline is switched off. 1: The last line (independent from `TDH') in the destination area is filled with a constant CLUT1 input (vector 0 of CLUT1) instead of the source bitmap input. Clipping on/off 00: Clipping is switched off. 01: Reserved. 10: Clipping is switched on. Pixels within the clipping area will be affected. 11: Clipping is switched on. Pixels outside the clipping area will be affected. Transparency Mode for Transfer `0': The complete area defined by instruction SDR and TDR is written to the destination. `1': Only these (4:4:4:2) pixels are written to the destination area, for which Bit TR1 = `0'. UN CL (1 ... 0) TRM Note: This bit is only relevant for 16-bit (4:4:4:2) RGB output formats Please also refer to Chapter 10.5.1. Users Manual 10 - 44 2000-06-15 SDA 6000 Display Generator Table 10-7 Bit TMODE (4 ... 0) (cont'd) Function Transfer Mode This mode is used to decide which transfer mode should be used. With this bit it is decided which input and which output format is used for transformation. For detailed information of the register settings please refer to Chapter 10.5.1 Italic This bit is used in transfer modes if 16-bit (4:4:4:2) RGB output mode is selected. `0': Italic is switched off. `1': Italic mode is enabled. Double Width during Transfer `0': Normal width is selected. `1': The memory transfer is stretched in horizontal direction on the output side. Double Height during Transfer `0': Normal height is selected. `1' The memory transfer is stretched in vertical direction on the output side. TQH must be set to `0'. Flash Definition This bit is used in transfer modes if output mode is in 16-bit (4:4:4:2) format for TTX. This bit is used to replace one of the 16 output bits. Please refer to Chapter 10.5.1. Bits Flash (1 ... 0) describe the flash phase for memory transfer modes: `00': slow rate (1 Hz) `01': Fast rate flash (2 Hz) Phase 1 `10': Fast rate flash (2 Hz) Phase 2 `11': Fast rate flash (2 Hz) Phase 3 IT TDW TDH FLA(1 ... 0) Users Manual 10 - 45 2000-06-15 D/A Converter SDA 6000 D/A Converter 11 D/A Converter M2 uses a 3 x 6-bit voltage D/A converter to generate analog RGB output signals with a nominal amplitude of 0.7 V (also available: 0.5 V, 1.0 V and 1.2 V) peak to peak. Two different modes are available in order to allow the reduction of power consumption for applications which require a lower RGB bandwidth. 11.1 DACCON 15 - Register Description Reset Value: 0005H 13 - 14 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 BWC 1 0 RGBGAIN (1..0) rw rw Bit RGBGAIN (1 ... 0) Function Gain Adjustment of RGB Converter. The user can change the output gain of the DAC. 00: 0.5 V 01: 0.7 V 10: 1.0 V 11: 1.2 V Bandwidth Control 0: The effective bandwidth of the DAC is set to 50 MHz 1: The effective bandwidth of the DAC is set to 32 MHz. This reduces the current consumption of analog supply. BWC Users Manual 11 - 3 2000-06-15 Slicer and Acquisition SDA 6000 Slicer and Acquisition 12 12.1 Slicer and Acquisition General Function M2 provides a full digital slicer including digital H- and V-sync separation and digital sync processing. The acquisition interface is capable to process on all known data services starting from line 6 to line 23 for TV (Teletext, VPS, CC, G+, WSS) as well as any full channel services. Four different framing codes (two of them programmable from field to field) are available for each field. Digital signal processing algorithms are applied to compensate various disturbance mechanisms. These are: * Noise measurement and compensation. * Attenuation measurement and compensation. * Group delay measurement and compensation. Note: Thus, M2 is optimized for precise data clock recovery and error free reception of data widely unaffected from noise and the currently valid channel characteristics. Two slicers with separated A/D converters and separated CVBS inputs are implemented. The first one is a full service slicer. The second one is a slicer which supports only the capturing of WSS data. Both CVBS inputs contain an on-chip clamping circuit. The integrated A/D converters are 7 bit video converters running at the internal frequency of 33.33 MHz. The sliced data is synchronized to the frequency of the clock-run-in of the actual data service and to the framing code of the data stream, framing code checked and written to a programmable VBI buffer in the external memory. After line 23 is received an interrupt can be given to the microcontroller. The microcontroller starts to process the data of this buffer. That means, the data is error checked by software and stored in the memory in the appropriate data base format. To improve the signal quality the slicer control logic generates horizontal and vertical windows in which the reception of the framing code is allowed. The framing code can be programmed for each line individually, so that in each line a different service can be received. For VPS and WSS the framing code is hardwired. In a special mode the framing code can be bypassed, so that all incoming data will be stored in the VBI buffer. The framing code check can then be made by software. All following acquisition tasks are performed by the internal controller, so in principal the data of every data service can be acquired. 12.2 Slicer Architecture The slicer is composed of five main blocks: * The full service slicer (Slicer 1) * The WSS only slicer (Slicer 2) * The H/V synchronization for full service slicer (Sync 1) Users Manual 12 - 3 2000-06-15 SDA 6000 Slicer and Acquisition * The H/V synchronization for WSS only slicer (Sync 2) * The acquisition interface Slicer 2 (WSS only Slicer) Sync 2 CVBS2 Data Separation D-PLL H/V Sync Sep. + Timing HS2_IR H-PLL VS2_IR Slicer 1 (Full Service Slicer) Sync 1 HS1_IR H/V Sync Sep. + Timing Data Separation Acquisition Interface VS1_IR H-PLL L23_IR CC_IR CVBS1 Noise Attenua. Group-D. Compen. D-PLL FC-Check & S/P Converter Address Generation To/from Memory Noise Attenua. Group-D. Measur. Parameter Buffer UEB11191 Figure 12-1 Block Diagram of Digital Slicer and Acquisition Interface Users Manual 12 - 4 2000-06-15 SDA 6000 Slicer and Acquisition 12.2.1 Distortion Processing For the full service slicer the digital bit stream is applied to a circuitry which corrects transmission distortion. In order to apply the correct counter-measures, a signal evaluation is done in parallel. This measurement device can detect the following distortions. Noise The noise measurement unit incorporates two different algorithms. Both algorithm are using the value between two equalizing pulses which corresponds to the black level. As the black level is known to the system a window is placed between two equalizing pulses of line four. The first algorithm compares successive samples inside a window placed in line 4. The difference between this samples is measured and a flag is set as soon as this difference over several TV lines is greater than a specified value. This algorithm is able to detect higher frequency noise (e.g. with noise). The second algorithm measures the difference between the black value and the actual sampled value inside this window. As soon as this difference over several TV lines is greater than a specified value a second flag is set. This algorithm is sensitive against low frequency noise as it is known from cochannel distortion. Both flags can be used to optimize the correcting circuit characteristic in order to achieve best reception performance. Frequency Attenuation During signal transmission the CVBS can be attenuated severely. This attenuation normally is frequency depending. That means that the higher the frequency the stronger the attenuation. As the clock-run-in (from now on CRI) for teletext represents the highest possible frequency (3.5 MHz) it can be used to measure the attenuation. As only strong negative attenuation causes problems during data slicing a flag is needed to notify highly negative attenuation. If this flag is set a special peaking filter is switched on in the datapath. Group Delay Quite often the data stream is corrupted because of group delay distortion introduced by the transmission channel. The teletext framing code (E4H) is used as a reference for measurement. The delay of the edges inside this code can be used to measure the group delay distortion. The measurement is done every teletext line and filtered over several lines. It can be detected whether the signal has positive, negative or no group delay distortions. Two flags are set accordingly. By means of these two flags an allpass contained in the correcting circuit is configured to compensate the positive or negative group delays. All of the above filters ca be individually disabled, forced or set to an automatic mode via control registers. Note: Slicer 2 does not have any compensation circuits. Users Manual 12 - 5 2000-06-15 SDA 6000 Slicer and Acquisition 12.2.2 Data Separation Parallel to the signal analyses and distortion compensation a filter is used to calculate the slicing level. The slicing level is the mean-value of the CRI. As the teletext is coded using the NRZ format, the slicing level can not be calculated outside the CRI and is therefore frozen after CRI. Using this slicing level the data is separated from the digital CVBS signal. The result is a stream of zeros and ones. In order to find the logical zeros and ones which have been transmitted, the data clock needs to be recovered as well. Therefore a digital data PLL (D-PLL) is synchronized to the data clock during CRI using the transitions in the sliced data stream. For TV-mode this D-PLL is also frozen after CRI, during VCR-mode it is tuned throughout the line using a slow time constant. Timing informations for freezing the slicing level, stopping the D-PLL and other actions are generated by the timing circuit. It generates all control signals which are dependent on the data start. In order to improve the reception performance the actual measured slicing level for each line is stored in the VBI-buffer. Using this slicing level the user is able to average the value over several fields for each data line by means of software filtering. If the averaged value becomes stable this value can be used for slicing instead of the internally calculated slicing level (for further information see RAM-register description). For data separation the WSS slicer (slicer 2) uses the same algorithms as the full service slicer. 12.3 H/V-Synchronization Slicer and acquisition interface need many signals synchronized to the incoming CVBS (e.g. line number, field or line start). Therefore a sync slicing level is calculated and the sync signal is sliced from the filtered digital CVBS signal. Using digital integration vertical and horizontal sync pulses are separated. The horizontal pulses are fed into a digital HPLL which has flywheel functionality. The H-PLL includes a counter which is used to generate all the necessary horizontal control signals. The vertical sync is used to synchronize the line counter from which the vertical control signals are derived. The synchronization block includes a watchdog which keeps control of the actual lock condition of the H-PLL.The watchdog can produce an interrupt (CC_IR) if synchronization has been lost. It could therefore be an indication for a channel change or missing input signal. Note: This H/V synchronization for the slicer 2 uses the same algorithms as described above. 12.4 Acquisition Interface The acquisition interface manages the data transfer between both slicers and memory. First of all a byte synchronization is performed (FC-check). Following this, the data is Users Manual 12 - 6 2000-06-15 SDA 6000 Slicer and Acquisition paralleled and shifted into memory as 16 bit words. In the other direction parameters are loaded from memory to the slicer. After every vertical sync, parameters needed for the field are downloaded and after every horizontal sync line parameters are downloaded. The parameters are used for slicer configuration. The data acquisition supports several features. The FC-checker is able to handle four different framing codes for one field. Two of these framing codes are programmable and could therefore be changed from field to field. The acquisition can be switched from normal mode (line 6 to 23) to full channel mode (line 6 to end of field). 12.4.1 FC-Check There are four FC's which are compared to the incoming signal. The first one is 8-bit wide and is loaded down with the field parameters. The second one is 16-bit wide and fixed to the FC of VPS. The third one is also 16-bit wide, but can be loaded with the field parameters. If the third one is used, the user can specify not only the FC but also a don'tcare mask. The fourth FC is reserved for WSS. The actual FC can be changed line by line. FC1 This FC should be used for all services with 8-bit framing codes (e.g. for TTX). The actual framing code is loaded down each field. The check can be done without any error tolerance or with a one bit error tolerance. Note: If FC1 = E4H this pattern is used as a reference for group delay measurement. FCVPS This FC is fixed to that of VPS. Only an error free signal will enable the reception of the VPS data line. Note: If VPS should be sliced in field 1 and TTX in field 2 the appropriate line parameters for line 16 have to be dynamically changed from field to field. FC3 This 16-bit framing code is loaded with the field parameters as well as a don't care mask. The incoming signal is compared to both, framing code and don't care mask. Further reception is enabled if all bits, which are not don't care, match the incoming data stream. FCWSS This FC is fixed to that of WSS. A special algorithm makes sure that the WSS-FC is detected even if the CVBS signal is coming from a video tape. Users Manual 12 - 7 2000-06-15 SDA 6000 Slicer and Acquisition No FC-check If FC-check is disabled, the data recording is triggered by the data start recognition. In this case the software needs to do the byte synchronization. FC-Check Select There is a two bit line parameter called FCSEL. With this parameter the user will be able to select which FC-Check is used for the actual line. If NORM is set to WSS the WSS FCcheck is used independently of FCSEL. 12.4.2 Interrupts Some events which occur inside the slicer, the sync separation or the acquisition interface can be used to trigger an interrupt. They are summarized in register ACQISN. The hardware sets the associated interrupt flag which must be manually reset by SW before the next interrupt can be accepted. All ACQ interrupts are bundled into one interrupt which is fed to the ACQ-interrupt node (ACQIC) of the controller. 12.4.3 VBI Buffer and Memory Organization Slicer and acquisition interface need parameters for configuration and they produce status information for the CPU. Some of these parameters and status bits are constant for a field. Those parameters are called field parameters. They are downloaded after the vertical sync of slicer 1. If the synchronization of slicer 1 is missing the vertical sync from slicer 2 is used to initialize the parameter download. Other parameters and status bits may change from line to line (e.g. data service dependent values). Those parameters are called line parameters. They are downloaded after each horizontal sync. The start address of the VBI (VBI = vertical blanking interval) buffer can be configured with special function register `STRVBI'. 32 16-bit words have to be reserved for every sliced data line. If 18 (in full channel mode 350) lines of data have been sent to memory no further acquisition takes place until the next vertical pulse appears and the H-PLL is still locked. That means if at least 1176 Bytes (22424 Bytes in full channel mode) are reserved for the VBI buffer no VBI overflow is possible. The acquisition can be started and stopped by the controller using bit `ACQON' of register STRVBI. The acquisition is stopped as soon as this bit changed to `0'. If the bit is changed back to `1' switching on of the acquisition is synchronized to the next V-pulse. The start address (Bit 13 ... 0 of register STRVBI) of the VBI buffer should only be changed if the acquisition is switched off. Users Manual 12 - 8 2000-06-15 SDA 6000 Slicer and Acquisition 15 STRVBI Send to slicer after V-Sync ACQFP0 ACQFP1 ACQFP2 Byte 1 8 7 Byte 0 0 Field Parameters Field Parameters Field Parameters Empty Empty Sliced WSS Data (Slicer 2) Sliced WSS Data (Slicer 2) Sliced WSS Data (Slicer 2) Sliced WSS Data (Slicer 2) Sliced WSS Data (Slicer 2) Sliced WSS Data (Slicer 2) Field Status Information from both Slicers Field Status Information from both Slicers Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Status 1 (of Line 6) Data byte 1 Data byte 0 Data byte 3 Data byte 2 Data byte 5 Data byte 4 Line Status 2 (of Line 6) Empty Empty Empty Empty Empty Empty Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Parameters for Slicer 1 Line Status 1 (of Line 7) Data Data Data and so on Data Data Data UED11192 Write to memory after V-Sync VBI Start Line 6 Send to slicer after V-Sync Send to memory after detecting a FC (if no FC has been detected after FCwin went inactive) ACQFP3 ACQFP4 ACQFP5 ACQFP6 ACQFP7 ACQFP8 ACQFP9 ACQFP10 ACQLP0 ACQLP1 ACQLP2 ACQLP3 ACQLP4 32 16 Bit Words ACQLP5 Last information for Line 6 VBI Start Line 7 Send to slicer after H-Sync Send to memory after detecting a FC (if no FC has been detected after FCwin went inactive) ACQLP0 ACQLP1 ACQLP2 ACQLP3 ACQLP4 Figure 12-2 VBI Buffer: General Structure 12.5 Register Description The acquisition interface has only two SFR Registers. The line and field parameters are stored in the RAM (RAM Registers). They have to be initialized by software before starting the acquisition. Users Manual 12 - 9 2000-06-15 SDA 6000 Slicer and Acquisition Special Function Registers: STRVBI 15 ACQ ON Reset Value: 0400H 13 12 11 10 9 8 7 6 5 4 3 2 1 0 14 0 VBIADR(23..10) Bit ACQON Function Enable Acquisition 0: The ACQ interface does not access memory (immediately inactive) 1: The ACQ interface is active and writes data to memory (switching on is synchronous to V) Define the 14 MSB's of the start address of the VBI buffer. The VBI buffer location can be aligned with any 1 KByte memory segment. Reset Value: 0000H 13 0 VBIADR (23 ... 10) ACQISN 15 0 14 0 12 0 11 10 9 8 L23_ IR 7 HS2_ IE 6 HS2_ IR 5 VS2_ IE 4 VS2_ IR 3 HS1_ IE 2 HS1_ IR 1 VS1_ IE 0 VS1_ IR CC_IE CC_IR L23_ IE rw Bit VS1_IR Function rw rw rw rw rw rw rw rw rw rw rw VS interrupt. The vertical sync impulse can be used to have field synchronization for the software. (VS of slicer 1 is used). 0: No request pending. 1: This source has raised an interrupt request. Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. HS interrupt. The horizontal sync impulse can be used to implement a software line counter. (HS of slicer 1 is used). 0: No request pending. 1: This source has raised an interrupt request. VS1_IE HS1_IR Users Manual 12 - 10 2000-06-15 SDA 6000 Slicer and Acquisition Bit HS1_IE Function Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. VS interrupt. The vertical sync impulse can be used to have field synchronization for the software. (VS of slicer 2 is used). 0: No request pending. 1: This source has raised an interrupt request. Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. HS interrupt. The horizontal sync impulse can be used to implement a software line counter. (HS of slicer 2 is used). 0: No request pending. 1: This source has raised an interrupt request. Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. Line 23 Interrupt.Tells the controller that line 23 of the VBI is sliced (Slicer 1 is used). 0: No request pending. 1: This source has raised an interrupt request. Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. Channel Change Indicator The H-PLL has lost the synchronization. (Slicer 1 is used). 0: No request pending. 1: This source has raised an interrupt request. VS2_IR VS2_IE HS2_IR HS2_IE L23_IR L23_IE CC_IR Note: Also refer to status bits STAB1 or VDOK1 CC_IE Interrupt Enable Bit 0: Disables the interrupt. 1: Enables the interrupt. Note: The interrupt request flags of the ACQ interrupt subnode have to be cleared by software within the interrupt service routine. Users Manual 12 - 11 2000-06-15 SDA 6000 Slicer and Acquisition 12.5.1 RAM Registers Field Parameters All field parameters are updated once in a field. This means that the status information written from the acquisition interface to the memory at that time only represents a snapshot of the status. Hardware ensures that field parameters are updated even if only one of the two CVBS signals has a valid sync timing. So it is assured that even if CVBS1 is not available data of CVBS2 still can be sliced. ACQFP0 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: XXXXH 3 2 1 0 FC3(15..0) Bit FC3 (15 ... 0) Function Framing code 3 Bit 15: First received bit of FC. Bit 0: Last received bit of FC. Reset Value: XXXXH 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACQFP1 15 14 FC3MASK(15..0) Bit FC3MASK (15 ... 0) Function Mask for Framing code 3 Bit 15: Mask for first received bit of FC. Bit 0: Mask for last received bit of FC. Users Manual 12 - 12 2000-06-15 SDA 6000 Slicer and Acquisition ACQFP2 15 14 13 12 11 10 9 8 7 AGD ON Reset Value: XXXXH 6 AFR ON 5 ANO OM 4 0 3 0 2 0 1 0 0 FULL FC1(7..0) Bit FC1 (7 ... 0) AGDON Function Framing code 1 Bit 7: First received bit of FC Bit 0: Last received bit of FC Automatic group delay compensation 0: Automatic compensation Off 1: Automatic compensation On (Automatic: Measurement Depending Compensation) Automatic frequency depending attenuation compensation 0: Automatic compensation Off 1: Automatic compensation On (Automatic: measurement depending compensation) Automatic noise compensation 0: Automatic compensation Off 1: Automatic compensation On (Automatic: measurement depending compensation) 0: 1: Full channel mode off Full channel mode on AFRON ANOON FULL Note: Don't forget to reserve enough memory for the VBI buffer and to initialized the appropriate line parameters. Users Manual 12 - 13 2000-06-15 SDA 6000 Slicer and Acquisition ACQFP3 15 14 13 0 Reset Value: XXXXH 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 WSS2 WSS2 OK _ACK WSS2_DATA(83..80) Bit WSS2OK Function 0: No new WSS data from slicer 2 is available 1: New WSS data from slicer 2 is available (written to memory by ACQ-interface) WSS data from slicer 2 are the same as in last slicer 1 field New WSS data from slicer 2 received WSS2_ACK 0: 1: WSS2_ DATA (83 ... 80) ACQFP4 15 14 13 12 4 bits of sliced data of slicer 2 (WWS2_DATA(83) = first received bit) (written to memory by ACQ-interface) Note: See also ACQFP4 t0 ACQFP8 Reset Value: XXXXH 11 10 9 8 7 6 5 4 3 2 1 0 WSS2_DATA(79..64) Bit WSS2_ DATA (79 ... 64) Function 16 bits of sliced data of slicer 2 (written to memory by ACQ-interface). Note: See also ACQFP3 and ACQFP5 to ACQFP8 Users Manual 12 - 14 2000-06-15 SDA 6000 Slicer and Acquisition ACQFP5 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: XXXXH 3 2 1 0 WSS2_DATA(63..48) Bit WSS2_ DATA (63 ... 48) ACQFP6 15 14 13 Function 16 bits of sliced data of slicer 2 (written to memory by ACQ-interface). Note: See also ACQFP3, ACQFP4, ACQFP6 to ACQFP8 Reset Value: XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 WSS2_DATA(47..32) b Bit WSS2_ DATA (47 ... 32) ACQFP7 15 14 13 Function 16 bits of sliced data of slicer 2 (written to memory by ACQ-interface). Note: See also ACQFP3 to ACQFP5 and ACQFP7 to ACQFP8 Reset Value: XXXXH 12 11 10 9 8 7 6 5 4 3 2 1 0 WSS2_DATA(31..16) Bit WSS2_ DATA (31 ... 16) Function 16 bits of sliced data of slicer 2 (written to memory by ACQ-interface). Note: See also ACQFP3 to ACQFP6 and ACQFP8 Users Manual 12 - 15 2000-06-15 SDA 6000 Slicer and Acquisition ACQFP8 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: XXXXH 3 2 1 0 WSS2_DATA(15..0) Bit WSS2_ DATA (15 ... 0) ACQFP9 15 0 Function 16 bits of sliced data of slicer 2 (WWS2_DATA(0) = last received bit) (written to memory by ACQ-interface). Note: See also ACQFP3 to ACQFP7 Reset Value: XXXXH 13 0 14 0 12 0 11 0 10 9 8 7 6 5 NOIS E(0) 4 GRD ON 3 GRD SIGN 2 1 0 FIELD 2 STAB VOK 1 1 FIELD FREA NOIS 1 TTF E(1) STAB VOK 2 2 Bit STAB1 (status bit) VOK1 (status bit) Function 0: H-PLL of slicer 1 not locked 1: H-PLL of slicer 1 locked (Written to memory by ACQ-interface) Vertical sync watchdog of slicer 1 0: V-sync of slicer 1 not stable 1: V-sync of slicer 1 stable (Written to memory by ACQ-interface) 0: Actual field of slicer 1 is field 1 1: Actual field of slicer 1 is field 2 (Written to memory by ACQ-interface) Frequency depending attenuation measurement (Field indicator) High frequency CVBS1components (around 3.5 MHz) are strongly damped (6 to 9 dB) compared to lower frequency CVBS1 components 0: no frequency depending attenuation has been detected during the last field 1: for at least one text line during the last field frequency depending attenuation has been detected. (Written to memory by ACQ-interface) FIELD1 (status bit) FREATTF (status bit) Users Manual 12 - 16 2000-06-15 SDA 6000 Slicer and Acquisition Bit NOISE (1 ... 0) (status bit) Function Noise and co-channel detector of slicer 1 00: No noise and no co-channel-distortion has been detected. 01: No noise but co-channel-distortion has been detected. 10: Noise but no co-channel-distortion has been detected. 11: Strong noise has been detected. (Written to memory by ACQ-interface) Group delay detector of slicer 1 0: No group delay distortion detected 1: Group delay distortion detected (Written to memory by ACQ-interface) 0: If group delay distortion has been detected it was positive 1: If group delay distortion has been detected it was negative (Written to memory by ACQ-interface, CVBS input of slicer 1 is used) 0: H-PLL of slicer 2 not locked 1: H-PLL of slicer 2 locked (Written to memory by ACQ-interface) Vertical sync watchdog of slicer 2 0: V-sync of slicer 2 not stable 1: V-sync of slicer 2 stable (Written to memory by ACQ-interface) 0: Actual field of slicer 2 is field 1 1: Actual field of slicer 2 is field 2 (Written to memory by ACQ-interface) Reset Value: XXXXH 13 0 GRDON (status bit) GRDSIGN (status bit) STAB2 (status bit) VOK2 (status bit) FIELD2 (status bit) ACQFP10 15 0 14 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 LEOFL(11.0) Bit LEOFLI (11 ... 0) Function This value is the output of the filter of the H-PLL of slicer 1 and represents the actual horizontal period of CVBS1 in 33.33 MHz clock cycles. This information can be used to measure the actual line frequency of the CVBS signal. Users Manual 12 - 17 2000-06-15 SDA 6000 Slicer and Acquisition Line Parameters Note: Line parameters only work on slicer 1 and have no influence on slicer 2. ACQLP0 15 14 13 12 11 10 9 8 7 6 5 4 Reset Value: XXXXH 3 2 1 0 DINCR(15..0) Bit DINCR (15 ... 0) Function Specifies the frequency of the D-PLL of slicer 1. This parameter is used to configure the D-PLL output frequency according to the service used. DINCR = fdata x 218 / 33.33 MHz fdata [MHz] 6.9375 5.7273 5.0 1.006993 ACQLP1 15 0 DINCR 54559 45041 39321 7920 Reset Value: XXXXH 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 2 1 0 NOI ON ACCU PLLT LOWP ON ON ON PFIL GDPO GDNO FRE ON N N ON Users Manual 12 - 18 2000-06-15 SDA 6000 Slicer and Acquisition Bit ACCUON Function Accumulator on Improves slicing level calculation under noisy conditions. If noise has been detected during automatic mode or if the bit NOION has been set the internal slicing level calculation can be improved by setting this bit. 0: Standard slicing level calculation 1: Improved slicing level calculation (improvement depends also on parameter ALENGTH) PLL tune on If noise has been detected during automatic mode or if the bit NOION has been set the data clock recovery PLL can be tuned throughout the line by setting this bit. 0: PLL is frozen after clock run in 1: PLL is tuned throughout the line Low Pass On If noise has been detected during automatic mode or if the bit NOION has been set a special low pass can be switched into the signal pass by setting this bit (useful if mainly high frequency noise above 3.5 MHz is present). 0: Low pass is not used 1: Low pass is used Pre Filter On If noise has been detected during automatic mode or if the bit NOION has been set a second filter can be switched into the signal pass by setting this bit (also useful if mainly high frequency noise above 3.5 MHz is present). 0: Low pass is not used. 1: Low pass is used. 0: 1: 0: 1: 0: 1: Group delay compensation depends on AGDON Positive group delay compensation is always on Group delay compensation depends on AGDON Negative group delay compensation is always on Frequency depending attenuation compensation depends on AFRON Frequency depending attenuation compensation is always on Noise compensation depends on ANOON Noise compensation is always on PLLLON LOWPON PFILLON GDPON GDNON FREON NOION 0: 1: Users Manual 12 - 19 2000-06-15 SDA 6000 Slicer and Acquisition ACQLP2 15 FC1 ER Reset Value: XXXXH 13 12 11 10 9 8 CLKDIV(2..0) 14 7 6 5 NORM(2..0) 4 3 2 1 VCR 0 0 MLENGTH(2..0) ALENGTH (1..0) FCSEL(1..0) Bit FC1ER Function Error tolerance of FC1 check 0: No error allowed 1: One error allowed For noise suppression reasons a median filter has been introduced after the actual data separation because of oversampling successive samples could be averaged. Therefore an odd number of sliced successive samples is taken and if the majority are `1' a `1' is sliced otherwise a `0'. MLENGTH specifies how many samples are taken. MLENGTH Number of samples 000 1 001 3 010 5 011 7 100 9 101 11 110 13 111 15 If noise has been detected or if NOISEON = 1, the output of the slicing level filter is further averaged by means of an accumulation (arithmetic averaging). ALENGTH specifies the number of slicing level filter output values used for averaging. The accumulation clock depends on CLKDIV. ALENGTH 00 01 10 11 Number of Slicing Level Output Values used for Averaging 2 4 8 16 MLENGTH (2 ... 0) ALENGTH (1 ... 0) Users Manual 12 - 20 2000-06-15 SDA 6000 Slicer and Acquisition Bit CLKDIV Function The slicing level filter needs to find the DC value of the CVBS during CRI. In order to do this it should suppress at least the CRI frequency. As different services use different data frequencies the CRI frequency will be different as well. Therefore the filter characteristic needs to be shifted. This can be done by using different clocks for the filter. The filter itself shows sufficient suppression for frequencies between 0.0757 x SLCLK and 0.13 x SLCLK (SLCLK is the actual filter clock and corresponds to slicer 1) CLKDIV 000 001 010 011 100 101 110 111 SLCLK 1 x fs 1/2 x fs 1/3 x fs 1/4 x fs 1/5 x fs 1/6 x fs 1/7 x fs 1/8 x fs Note: fs = 33.33 MHz NORM Most timing signals are closely related to the actual data service used. Therefore 3 bits specify the service received in the actual line. NORM 000 001 010 011 100 101 110 111 Service TXT NABTS VPS WSS CC G+ reserved no data service Users Manual 12 - 21 2000-06-15 SDA 6000 Slicer and Acquisition Bit FCSEL Function There are three different framing codes which can be used for each field. The framing code used for the actual line is selected with FCSEL (corresponds to slicer 1). FCSEL 00 01 10 11 VCR FC FC1 FC2 FC3 No FC-check (all data are dumped to the VBI buffer) This bit is used to change the behavior of the D-PLL and H-PLL. 0: D-PLL tuning is stopped after CRI; H-PLL -> slow time constant 1: D-PLL is tuned throughout the line; H-PLL -> fast time constant Reset Value: XXXXH 13 12 11 10 9 8 7 SLSS ACQLP3 15 14 6 5 4 3 SSL(6..0) 2 1 0 Bit SLSS Function Slicing Level Source Selector The slicer allows the use of an internal calculated slicing level or an external set slicing level. 0: Internal calculated slicing level is used. 1: External set slicing level is used. Set Slicing Level If the bit SLSS is set the slicer is using the value of SSL as slicing level instead of the internal calculated slicing level. The slicing level output in parameter MSL is never the less the internal calculated value. SSL(6 ... 0) Users Manual 12 - 22 2000-06-15 SDA 6000 Slicer and Acquisition ACQLP4 15 FREA TTL Reset Value: XXXXH 13 12 11 MSL(6..0) 14 10 9 8 7 6 5 4 3 2 1 0 PERRP(5..0) TLDE FCOK Bit FREATTL Function Frequency Depending Attenuation Measurement (Line indicator) High frequency-CVBS1-components (around 3.5 MHz) are strongly damped (6 to 9 dB) compared to lower frequency-CVBS1-components 0: no frequency depending attenuation has been detected for the following line 1: strong frequency depending attenuation has been detected for the following line (Written to memory by ACQ-interface) Measured Slicing Level The value represents the slicing level which has been measured for the current data line. The value can be used to calculate a better slicing level especially for noisy signals by means of software averaging algorithms. The improved slicing level can be set for the following fields by writing to parameter SSL. Phase Error Watch Dog Preliminary (detection of test line CCIR331a or b) The value shows how often in a line the internal PLL found strong phase deviations between PLL and sliced data. The value can be used to detect test line CCIR331a or b. This value is only preliminary as an exact result is only available at the end of each line. For the exact value see PERR at ACQLP5. PERRP < 32? No test line. PERRP > 31? Test line CCIR331a or b detected Test Line Detected (CCIR17 or CCIR18 or CCIR330) 0: No test line of the above mentioned test lines has been detected 1: The following data has most likely be sliced from a test line and should therefor be ignored. Framing Code Received 0: No framing code has been detected (no new data has been written to memory) 1: The selected framing code has been detected (new data has been written to memory MSL(6 ... 0) PERRP (5 ... 0) TLDE FCOK Users Manual 12 - 23 2000-06-15 SDA 6000 Slicer and Acquisition ACQLP5 15 0 Reset Value: XXXXH 13 0 14 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0 PERR(5..0) Bit PERR (5 ... 0) Function Phase Error Watch Dog (detection of test line CCIR331a or b) This is the exact phase error watch dog output for the current line. The value shows how often in a line the internal PLL found strong phase deviations between PLL and sliced data. The value can be used to detect test line CCIR331a or b. PERR < 32? No test line. PERR > 31? Test line CCIR331a or b detected Users Manual 12 - 24 2000-06-15 SDA 6000 Slicer and Acquisition 12.5.2 Recommended Parameter Settings TTX VPS 0 0 1 0 0 0 1 1 1 1 0 0 45041 0 2 2 0 2 1 0 don't care don't care don't care WSS 0 0 1 0 0 0 1 1 1 1 0 0 39321 0 7 2 2 3 2 0 don't care don't care don't care CC 0 0 1 0 0 0 1 1 1 1 0 0 7864 0 7 2 5 4 2 0 don't care 3 65472 G+ 0 0 1 0 0 0 1 1 1 1 0 0 7920 0 7 2 5 5 2 0 don't care 1261 63488 AGDON AFRON ANOON GDPON GDNON FREON PFILON LOWPON PLLTON ACCUON NOION FULL DINCR FC1ER MLENGTH ALENGTH CLKDIV NORM FCSEL VCR FC1 FC3 FC3MASK 1 1 1 0 0 0 0 0 0 0 0 0 54559 0 1 2 0 0 0 0 228 don't care don't care Users Manual 12 - 25 2000-06-15 Register Overview SDA 6000 Register Overview 13 Register Overview This section summarizes all SFR and ESFR registers, which are implemented in M2 and explains the description format which is used in the previous chapters to describe the functionality of the SFRs. Display generators and slicers are mainly programmed via RAM registers which are not mentioned in this chapter, due to their variable position in the RAM. RAM registers are principally undefined after reset. For easy reference the registers are ordered according to two different keys: * Ordered by their functional context * Ordered by register address, to find the location of a specific register. 13.1 Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register. The example below shows how to interpret these details. A register looks like this: REG_NAME 15 - Reset Value: ****H 12 - 14 - 13 - 11 - 10 - 9 - 8 - 7 - 6 write only 5 read only 4 std bit 3 hw bit 2 1 bitfield(2:0) 0 w r rw rw rw Bit bit(field) name Function Explanation of bit(field)name Description of the functions controlled by this bit(field). REG_NAME Name of this register. **** rw Register contents after reset. 0/1: defined value, `X': undefined after power up. Bits that are set/cleared by hardware are marked with a shaded access box. Read only register. Register can be read and written. Reserved register bit. Reading such bits delivers an undefined value. If such a bit is written then only `0' is allowed. r rw - Users Manual 13 - 3 2000-06-15 SDA 6000 Register Overview 13.2 CPU General Purpose Registers (GPRs) The GPRs form the register bank with which the CPU works. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the internal RAM. All GPRs are bit-addressable. Name R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Physical Address (CP) + 0 (CP) + 2 (CP) + 4 (CP) + 6 (CP) + 8 8-Bit Description Address F0H F1H F2H F3H F4H CPU General Purpose (Word) Register R0 CPU General Purpose (Word) Register R1 CPU General Purpose (Word) Register R2 CPU General Purpose (Word) Register R3 CPU General Purpose (Word) Register R4 CPU General Purpose (Word) Register R5 CPU General Purpose (Word) Register R6 CPU General Purpose (Word) Register R7 CPU General Purpose (Word) Register R8 CPU General Purpose (Word) Register R9 CPU General Purpose (Word) Register R10 CPU General Purpose (Word) Register R11 CPU General Purpose (Word) Register R12 CPU General Purpose (Word) Register R13 CPU General Purpose (Word) Register R14 CPU General Purpose (Word) Register R15 Reset Value XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH XXXXH (CP) + 10 F5H (CP) + 12 F6H (CP) + 14 F7H (CP) + 16 F8H (CP) + 18 F9H (CP) + 20 FAH (CP) + 22 FBH (CP) + 24 FCH (CP) + 26 FDH (CP) + 28 FEH (CP) + 30 FFH The first 8 GPRs (R7 ... R0) may also be accessed via the byte. Other than with SFRs, writing to a GPR byte does not affect the other byte of the respective GPR. The respective half of the byte-accessible registers receive special names: Users Manual 13 - 4 2000-06-15 SDA 6000 Register Overview Name RL0 RH0 RL1 RH1 RL2 RH2 RL3 RH3 RL4 RH4 RL5 RH5 RL6 RH6 RL7 RH7 Physical Address (CP) + 0 (CP) + 1 (CP) + 2 (CP) + 3 (CP) + 4 (CP) + 5 (CP) + 6 (CP) + 7 (CP) + 8 (CP) + 9 8-Bit Description Address F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H CPU General Purpose (Byte) Register RL0 CPU General Purpose (Byte) Register RH0 CPU General Purpose (Byte) Register RL1 CPU General Purpose (Byte) Register RH1 CPU General Purpose (Byte) Register RL2 CPU General Purpose (Byte) Register RH2 CPU General Purpose (Byte) Register RL3 CPU General Purpose (Byte) Register RH3 CPU General Purpose (Byte) Register RL4 CPU General Purpose (Byte) Register RH4 CPU General Purpose (Byte) Register RL5 CPU General Purpose (Byte) Register RH5 CPU General Purpose (Byte) Register RL6 CPU General Purpose (Byte) Register RH6 CPU General Purpose (Byte) Register RL7 CPU General Purpose (Byte) Register RH7 Reset Value XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH (CP) + 10 FAH (CP) + 11 FBH (CP) + 12 FCH (CP) + 13 FDH (CP) + 14 FEH (CP) + 15 FFH 13.3 Registers Ordered by Context The following table lists all SFRs which are implemented in the M2 grouped by their context. Their actual address can be seen in the next chapter. Table 13-1 Name Description Physical 8-Bit Reset Address Address Value FFB2H F0B4H F0B0H F0B2H FFB0H D9H 5AH 58H 59H D8H 0000H 0000H 0000H 0000H 0000H SSC Registers SSCCON SSCBR SSCTB SSCRB S0CON Control Register Baud Rate Timer Reload Register Transmit Buffer Register Receive Buffer Register Control Register ASC Registers Users Manual 13 - 5 2000-06-15 SDA 6000 Register Overview Table 13-1 Name (cont'd) Description Physical 8-Bit Reset Address Address Value F0B8H F1B8H FEB4H FEB6H FEAAH FEB0H FEB2H E810H E812H E814H E816H E818H E81AH E804H FFAEH FEAEH F1CCH F0D0H F0D2H F0D4H F0D6H F0CCH F0CEH 5CH DCH 5AH 5BH 55H 58H 59H -/-/-/-/-/-/-/D7H 57H E6H 68H 69H 6AH 6BH 66H 67H E4H EFH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 000XH 0000H 0003H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H S0ABSTAT Autobaud Status Register S0ABCON S0BG S0FDV S0PMW S0TBUF S0RBUF ICCFG2) ICCON2) ICST2) ICADR2) ICRTBL2) ICRTBH 2) 2) Autobaud Control Register Baud Rate Timer Reload Register Fractional Divider Register IrDA Pulse Mode and Width Register Transmit Buffer Register Receive Buffer Register I2C Configuration Register I2C Control Register I2C Status Register I2C Address Register I2C Receive/Transmit Buffer (Low Word) I C Receive/Transmit Buffer (High Word) I C Port Input Selection Register Control Register Timer Register Control Register Prescaler Timer Reload Prescaler Timer T14 Count Register Low Word Count Register High Word Reload Register Low Word Reload Register High Word 2 2 I2C Registers IICPISEL Watchdog Timer Registers WDTCON WDT RTCCON T14REL T14 RTCL RTCH RTCRELL RTCRELH RTCISNC ISNC Realtime Clock Registers RTC Interrupt Subnode Control (1st Level) F1C8H RTC Interrupt Subnode Control (2nd Level) F1DEH Users Manual 13 - 6 2000-06-15 SDA 6000 Register Overview Table 13-1 Name (cont'd) Description Physical 8-Bit Reset Address Address Value FF40H FF42H FF44H FF46H FF48H FE40H FE42H FE44H FE46H FE48H FE4AH FEA0H FEA2H FEA4H FF60H FF62H FF64H FF66H FF68H FF6AH FF88H FF8AH FF8CH FF8EH FF90H FF92H FF94H A0H A1H A2H A3H A4H 20H 21H 22H 23H 24H 25H 50H 51H 52H B0H B1H B2H B3H B4H B5H C4H C5H C6H C7H C8H C9H CAH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 2000-06-15 General Purpose Timer Registers (GPT1/2) T2CON T3CON T4CON T5CON T6CON T2 T3 T4 T5 T6 CAPREL ADDAT1 ADDAT2 ADCCON T2IC T3IC T4IC T5IC T6IC CRIC EX0IC EX1IC EX2IC EX3IC EX4IC EX5IC EX6IC Users Manual GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register GPT1 Timer 4 Control Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT2 Timer 5 Register GPT6 Timer 2 Register GPT1 Capture Reload Register ADC Data Register for Channel 1 and 2 ADC Data Register for Channel 3 and 4 ADC Control Register Timer 2 Interrupt Control Register Timer 3 Interrupt Control Register Timer 4 Interrupt Control Register Timer 5 Interrupt Control Register Timer 6 Interrupt Control Register CAPREL Interrupt Control Register External Interrupt Control Register 0 External Interrupt Control Register 1 External Interrupt Control Register 2 External Interrupt Control Register 3 External Interrupt Control Register 4 External Interrupt Control Register 5 External Interrupt Control Register 6 13 - 7 ADC Registers Interrupt Control Registers SDA 6000 Register Overview Table 13-1 Name EX7IC ADC1IC ADC2IC ADWIC SSCEIC SSCRIC SSCTIC S0EIC S0RIC S0TIC S0TBIC ABSTOIC ABSTAIC I2CTIC I2CPIC I2CTEIC ACQIC VSDISIC HSDISIC GAFIC RTCIC PECCLIC PECC0 PECC1 PECC2 PECC3 PECC4 (cont'd) Description External Interrupt Control Register 7 A/D Conversion Interrupt Control (Channel 1 + 2) A/D Conversion Interrupt Control (Channel 3 + 4) A/D Wake Up Interrupt SSC Error Interrupt Control SSC Receive Interrupt Control SSC Transmit Interrupt Control ASC Error Interrupt Control ASC Receive Interrupt Control ASC Transmit Interrupt Control ASC Transmit Buffer Interrupt Control ASC Autobaud Stop Interrupt Control ASC Autobaud Start Interrupt Control I2C Transfer Interrupt Control I2C Protocol Interrupt Control I2C Transmission End Interrupt Control Acquisition-Interrupt Control Display-Vertical-Sync Interrupt Control Display-Horizontal-Sync Interrupt Control Graphic Accelerator Interrupt Control Realtime Clock Interrupt Control PEC Link Interrupt Control PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register Physical 8-Bit Reset Address Address Value FF96H FF98H FF9AH F178H FF76H FF74H FF72H FF70H FF6EH FF6CH F19CH F17AH FF9EH F194H F18CH F184H F176H F174H F172H FF9CH F19EH F180H FEC0H FEC2H FEC4H FEC6H FEC8H CBH CCH CDH BCH BBH BAH B9H B8H B7H B6H CEH BDH CFH CAH C6H C2H BBH BAH B9H CEH CFH C0H 60H 61H 62H 63H 64H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 2000-06-15 PEC Interrupt Control Registers Users Manual 13 - 8 SDA 6000 Register Overview Table 13-1 Name PECC5 PECC6 PECC7 PECSN0 PECSN1 PECSN2 PECSN3 PECSN4 PECSN5 PECSN6 PECSN7 CLISNC (cont'd) Description PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Physical 8-Bit Reset Address Address Value FECAH FECCH FECEH 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH D4H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H PEC Segment Number Channel 0 Register FED0H PEC Segment Number Channel 1 Register FED2H PEC Segment Number Channel 2 Register FED4H PEC Segment Number Channel 3 Register FED6H PEC Segment Number Channel 4 Register FED8H PEC Segment Number Channel 5 Register FEDAH PEC Segment Number Channel 6 Register FEDCH PEC Segment Number Channel 7 Register FEDEH PEC Channel Link Interrupt Subnode Register Reset Configuration at Port 4 (read only) Port 2 Register Port 3 Register Port 4 Register Port 5 Register Port 6 Register Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 6 Open Drain Control Register Port 3 Open Drain Control Register Port 6 FFA8H Port Registers RP0H P2 P3 P4 P5 P6 DP2 DP3 DP6 ODP3 ODP6 P5BEN F108H FFC0H FFC4H FFC8H FFA2H FFCCH FFC2H FFC6H FFCEH F1C6H F1CEH 85H E0H E2H E4H D1H E6H E1H E3H E7H E3H E7H E1H 96H D0H XXH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Analog/Digital Input Enable Register Port 5 F1C2H ALTSEL0P6 Alternate Function Enable Register Port 6 F12CH Specific Control Registers STRVBI VBI Buffer Start Register F1A0H Users Manual 13 - 9 2000-06-15 SDA 6000 Register Overview Table 13-1 Name PXDEL ACQISN GPRGCRL DGCON SCR VLR BVCR EVCR HPR SDV SDH HCR PFR DACCON REDIR REDIR1 EBICON EBIDIR COMDATA RWDATA IOSR DCMPLL DCMPLH DCMPGL DCMPGH (cont'd) Description Pixel Delay Register Acquisition Interrupt Subnode Register Physical 8-Bit Reset Address Address Value F198H F1A2H CCH D1H D2H D3H 7DH D4H D5H 7BH 7CH D6H D7H D8H D9H DBH DAH DDH E5H DEH DFH 34H 35H 36H 6EH 6FH 70H 71H 0000H 0000H 0000H 0000H 0000H 0000H 0271H 0001H 0005H 0855H 0020H 0020H 1400H 00A4H 0005H 0000H 00FFH 0000H 0000H 0000H 0000H 0000H 0000H1) 0000H1) 0000H1) 0000H1) 2000-06-15 GAI Instruction Start Register (Low Word) F1A4H Display Generator Control Sync Control Register Vertical Line Register Begin of Vertical Clamping End of Vertical Clamping Horizontal Period Register Vertical Sync Delay Register Horizontal Sync Delay Register Horizontal Clamping Register Pixel Frequency Register RGB - DAC Control Register Memory Map Redirection Register Memory Map Redirection Register 1 Control Register for EBI Direct Access Register for EBI Communication Mode Data Register Read/Write Mode Data Register Communication Mode Status Register Hardware Trigger Range Comparison Lower Bound Extension of Register DCMPLL Hardware Trigger Range Comparison Upper Bound Extension of Register DCMPGL FEFAH F1A8H F1AAH FEF6H FEF8H F1ACH F1AEH F1B0H F1B2H F1B6H F1B4H F1BAH F1CAH F1BCH F1BEH F068H F06AH F06CH F0DCH F0DEH F0E0H F0E2H GPRGCRH GAI Instruction Start Register (High Word) F1A6H External Bus Interface Control Registers OCDS Registers Users Manual 13 - 10 SDA 6000 Register Overview Table 13-1 Name DCMP0L DCMP0H DCMP1L DCMP1H DCMP2L DCMP2H DTREVT DSWEVT DEXEVT DBGSR TFR (cont'd) Description Hardware Trigger Equal Comparison Register 0 Extension of Register DCMP0L Hardware Trigger Equal Comparison Register 1 Extension of Register DCMP1L Hardware Trigger Equal Comparison Register 2 Extension of Register DCMP2L Hardware Trigger Event Control Software Trigger Event Control External Trigger Event Control Debug Status Register Trap Flag Register Physical 8-Bit Reset Address Address Value F0E4H F0E6H F0E8H F0EAH F0ECH F0EEH F0F0H F0F4H F0F8H F0FCH FFACH FE18H FE1AH FE1CH FE1EH FF0CH FF14H FF16H FF18H FF1AH FF12H F1DCH F1D0H F014H F016H F018H 72H 73H 74H 75H 76H 77H 78H 7AH 7CH 7EH D6H 0CH 0DH 0EH 0FH 86H 8AH 8BH 8CH 8DH 89H EEH E8H 0AH 0BH 0CH 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H1) 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0400H 0000H 0000H 0000H 0000H 0000H System & CPU Registers ADDRSEL1 Address Select Register 1 ADDRSEL2 Address Select Register 2 ADDRSEL3 Address Select Register 3 ADDRSEL4 Address Select Register 4 BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 SYSCON SYSCON1 SYSCON2 XADRS1 XADRS2 XADRS3 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 CPU System Configuration Register CPU System Configuration Register 1 CPU System Configuration Register 2 External Address Select Register 1 External Address Select Register 2 External Address Select Register 3 Users Manual 13 - 11 2000-06-15 SDA 6000 Register Overview Table 13-1 Name XADRS4 XADRS5 XADRS6 XBCON1 XBCON2 XBCON3 XBCON4 XBCON5 XBCON6 DPP0 DPP1 DPP2 DPP3 MDH MDL MDC PSW STKUN STKOV SP CP CSP SCUSLC SCUSLS ZEROS ONES XPERCON EXISEL (cont'd) Description External Address Select Register 4 External Address Select Register 5 External Address Select Register 6 XBUS Control Register 1 XBUS Control Register 2 XBUS Control Register 3 XBUS Control Register 4 XBUS Control Register 5 XBUS Control Register 6 CPU Data Page Pointer 0 (10bits) CPU Data Page Pointer 1 (10bits) CPU Data Page Pointer 2 (10bits) CPU Data Page Pointer 3 (10bits) Physical 8-Bit Reset Address Address Value F01AH F01CH F01EH F114H F116H F118H F11AH F11CH F11EH FE00H FE02H FE04H FE06H 0DH 0EH 0FH 8AH 8BH 8CH 8DH 8EH 8FH 00H 01H 02H 03H 06H 07H 87H 88H 0BH 0AH 09H 08H 04H 60H 61H 8EH 8FH 12H EDH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0001H 0002H 0003H 0000H 0000H 0000H 0000H 0000H 0000H FC00H FC00H 0000H 0000H 0000H 0000H FFFFH 0000H 0000H 2000-06-15 CPU Multiply Divide Control Register High FE0CH Word CPU Multiply Divide Control Register Low FE0EH Word CPU Multiply Divide Control Register CPU Program Status Word CPU Stack Underflow Pointer Register CPU Stack Overflow Pointer Register CPU System Stack Pointer CPU Context Pointer CPU Code Segment Control Register Security Level Command Register Security Level Status Register Constant Value 0's Register (read only) Constant Value 1's Register (read only) X-Peripheral Control Register Alternative External Interrupt Selection FF0EH FF10H FE16H FE14H FE12H FE10H FE08H F0C0H F0C2H FF1CH FF1EH F024H F1DAH Users Manual 13 - 12 SDA 6000 Register Overview Table 13-1 Name EXICON OSCCON IDMANUF IDCHIP TM_LO TM_HI FOCON SYSCON3 1) 2) (cont'd) Description External Interrupt Control Oscillator Pad Control Register Manufacture ID Chip ID Hardware Testmode Register Low Hardware Testmode Register High SCU Register (no Function within M2) SCU Register (no Function within M2) Physical 8-Bit Reset Address Address Value F1C0H F1C4H F07EH F07CH FEFCH FEFEH FFAAH F1D4H E0H E2H 3FH 3EH 7EH 7FH D5H EAH 0000H 0001H XXXXH XXXXH 0000H 0000H 0000H 0000H OCDS related registers that are not reset during a controller reset. No 8-bit addresses provided for XBUS registers. 13.4 Registers Ordered by Address The following tables summarize the register symbols and their "short addresses". The physical address can be calculated by multiplying the short address by 2 and adding that value to FE00H for the SFR register area and adding F000H for the extended SFR area. Bit-addressable registers are highlighted in gray. Users Manual 13 - 13 2000-06-15 SDA 6000 Register Overview 13.4.1 Address 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H 80H 88H 90H 98H A0H A8H B0H B8H C0H C8H D0H D8H E0H E8H F0H F8H Registers in SFR Area + 00H DPP0 CP T2 ADDAT1 SOTBUF PECC0 PECSN0 PSW T2CON T2IC S0EIC CC4IC S0CON P2 R0 R8 + 01H DPP1 SP T3 ADDAT2 SORBUF PECC1 PECSN1 SYSCON T3CON T3IC SSCTIC CC5IC P5 SSCCON DP2 R1 R9 + 02H DPP2 STKOV T4 ADCCON S0BG PECC2 PECSN2 BUSCON1 T4CON T4IC SSCRIC CC6IC P3 R2 R10 + 03H DPP3 STKUN T5 S0FDV PECC3 PECSN3 BVCR BUSCON2 T5CON T5IC SSCEIC CC7IC DP3 R3 R11 + 04H CSP ADDRSEL1 T6 S0ABSTAT PECC4 PECSN4 EVCR BUSCON3 T6CON T6IC CC0IC ADC1IC CLISNC S0ABCON P4 R4 R12 + 05H reserved ADDRSEL2 CAPREL S0PMW PECC5 PECSN5 DGCON BUSCON4 CRIC ABSTOIC CC1IC ADC2IC FOCON reserved R5 R13 + 06H MDH ADDRSEL3 reserved PECC6 PECSN6 TM_LO BUSCON0 ZEROS S0TIC CC2IC GAFIC TFR P6 R6 R14 + 07H MDL ADDRSEL4 WDT PECC7 PECSN7 TM_HI MDC ONES S0RIC CC3IC ABSTAIC WDTCON DP6 R7 R15 Users Manual 13 - 14 2000-06-15 SDA 6000 Register Overview 13.4.2 Address 00H 08H 10H 18H 20H 28H 30H 38H 40H 48H 50H 58H 60H 68H 70H 78H 80H 88H 90H 98H A0H A8H B0H B8H C0H C8H D0H D8H E0H E8H F0H F8H Registers in ESFR Area + 00H reserved IDRT SSCTB SCUSLC T14REL DCMPGL DTREVT PECCLIC STRVBI SDH EXICON SYSCON2 R0 R8 + 01H reserved IDSCU SSCRB SCUSLS T14 DCMPGH HSDISIC ACQISN HCR P5BEN R1 R9 + 02H XADRS1 XPERCON reserved SSCBR RTCL DCMP0L DSWEVT XBCON1 VSDISIC I2CTEIC I2CTIC GPRGCRL DACCON OSCCON SYSCON3 R2 R10 + 03H XADRS2 IDMEM2 reserved RTCH DCMP0H XBCON2 ACQIC GPRGCRH PFR ODP3 R3 R11 + 04H XADRS3 COMDATA IDPROG reserved reserved reserved DCMP1L DEXEVT RP0H XBCON3 ADWIC PXDEL SCR reserved RTCISNC R4 R12 + 05H XADRS4 RWDATA IDMEM reserved DCMP1H XBCON4 VLR REDIR REDIR1 EXISEL R5 R13 + 06H CPUID XADRS5 reserved IOSR IDCHIP RTCRELL DCMPLL DCMP2L DBGSR XBCON5 ALTSEL0P6 + 07H XADRS6 reserved IDMANUF RTCRELH DCMPLH DCMP2H XBCON6 RTCIC SDV EBIDIR ODP6 ISNC R7 R15 I2CPIC S0TBIC HPR EBICON RTCCON SYSCON1 R6 R14 Users Manual 13 - 15 2000-06-15 Elelctrical Characteristics SDA 6000 Electrical Characteristics 14 14.1 Electrical Characteristics Absolute Maximum Ratings Note: The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 14-1 Parameter Supply voltage 3.3 V Supply voltage 2.5 V Analog supply voltage Storage temperature Electrostatic discharge Ambient Temperature TA = 0 C ... + 70 C Symbol Limit Values Unit min. max. Test Condition - - - - 100 pF, 1.5 k HBM VDD33 1-7 VDD25 1-2 VDDA 1-4 Tstg - - - - - 20 2000 4.0 3.0 3.0 125 - V V V C V 14.2 Table 14-2 Parameter Operating Range Operating Range Symbol Limit Values min. max. 70 3.6 2.75 2.75 1.5 C V V V W - - - - - 0 3.1 2.25 2.25 - Unit Test Condition Ambient temperature Supply voltage 3.3 V Supply voltage 2.5 V Analog supply voltage Total Power Consumption TA VDD33 1-7 VDD25 1-2 VDDA 1-4 Ptotal Note: In the operating range, the functions given in the circuit description are fulfilled. Users Manual 14 - 3 2000-06-15 SDA 6000 Electrical Characteristics 14.3 Table 14-3 Parameter DC Characteristics DC Characteristics Symbol Limit Values min. max. 150 mA all ports as inputs, fpixel = 50 MHz, 100 MHz bus configuration Unit Test Condition Supply Currents Digital supply current for 3.3 V domain I3.3 V - Digital supply current for 2.5 V domain Analog Power Supply Current I2.5 V - 150 mA fpixel = 50 MHz, 100 MHz bus configuration IANA - - 100 12 mA mA - Analog and digital supply Idle mode supply current IIDLE (with A/D wake up, RTC and External Interrupts in active state) Sleep mode supply current (RTC running) Power down mode supply current (RTC disabled) Input low voltage Input high voltage Output low voltage Output high voltage Leakage current Output Current Amplifier Transconductance Oscillation Frequency ISLEEP IPWDN - - 1.2 0.5 mA mA Analog and digital supply Analog and digital supply - - - - @ 0.5 V < Vin < (VIHNOM - 0.5 V) - - - I/O Voltages (valid for any pin unless otherwise stated) VIL VIH VIL VIH IIL IO - - 0.4 2.0 - 2.5 - - - 6.0 - 50 ppm 0.8 3.6 0.45 - 0.2 8 4.2 6.0 + 50 ppm V V V V A mA mS MHz Crystal Oscillator: XTAL1(input), XTAL2(output) CFB Users Manual 14 - 4 2000-06-15 SDA 6000 Electrical Characteristics Table 14-3 Parameter Duty Cycle High time Pin capacitance (XTAL1) Pin capacitance Input impedance Ext. coupling capacitance Source impedance Overall CVBS amplitude CVBS sync amplitude TXT data amplitude De-coupling Capacitors to VDDA at Pins CVBSi Pin capacitance Input impedance Ext. coupling capacitance Source impedance Overall CVBS amplitude CVBS sync amplitude TXT data amplitude De-coupling Capacitors to VDDA at Pins CVBSi CVBS-Input: CVBS2 Pin capacitance Input impedance Ext. coupling capacitance Source impedance Overall CVBS amplitude CVBS sync amplitude Users Manual DC Characteristics (cont'd) Symbol Limit Values min. - 45 50 - - - 10 - 0.75 0.18 0.3 - max. 55 - 3.5 - - 100 < 500 1.3 0.6 0.7 - % ns pF pF nF V V V nF - - - - - - - - - - Unit Test Condition tH CI CP ZP CCPL1,2 - CVBS-Input: CVBS1A (ADC_DIFF = 0; differential CVBS Input) 1/M - VCVBS VSYNC VDATA CDec_CPL CVBS-Input: CVBS1A (ADC_DIFF = 1; non-differential CVBS Input) CP ZP CCPL1 VCVBS VSYNC VDATA CDec_CPL - - 10 - 0.75 0.18 0.3 - - - 100 < 500 1.3 0.6 0.7 - pF nF V V V nF - - - - - - - 1/M - CP ZP CCPL - - - 10 - 0.75 0.18 14 - 5 - - 100 < 500 1.3 0.6 pF nF V V - - - - - 2000-06-15 1/M - VCVBS VSYNC SDA 6000 Electrical Characteristics Table 14-3 Parameter TXT data amplitude De-coupling Capacitors to VDDA at Pins CVBSi RGB-Outputs Load capacitance Output voltage swing RGB offset Rise/Fall Times DC Characteristics (cont'd) Symbol Limit Values min. max. 0.7 - V nF - - Unit Test Condition VDATA 0.3 CDec_CPL - CP Voutpp Uoffset tRF - 0.5 0.27 8.0 20 1.2 0.33 12.5 pF V V ns - available: 0.5 V; 0.7 V; 1.0 V; 1.2 V - 8.0 ns (50 MHz output BW) 12.5 ns (32 MHz output BW) - - - - - - Load resistance Diff. non-linearity Int. non-linearity Output current tracking Skew to COR, Blank Jitter to Horizontal Sync Reference Output Rise Time Output Fall Time Load Capacitance Address Bits: A10 to A15 Output Rise Time Output Fall Time Load Capacitance P4.(0 .. 5) Output Rise Time Output Fall Time Load Capacitance Users Manual RL - - - 10 - 0.5 - 0.5 - -5 - - 0.5 0.5 3 5 4 k LSB LSB % ns ns tskew tJit Address Bits: A0 to A9, RD, CSROM tr tf CL tr tf CL tr tf CL - - - - - - - - - 14 - 6 16 16 35 6 6 35 16 16 35 ns ns pF ns ns pF ns ns pF (10% - 90%) (10% - 90%) - (10% - 90%) (10% - 90%) - (10% - 90%) (10% - 90%) - 2000-06-15 SDA 6000 Electrical Characteristics Table 14-3 Parameter Data Bits: D0 to D15 Output Rise Time Output Fall Time Load Capacitance Pin capacitance Output Rise Time Output Fall Time Load Capacitance Pin capacitance MEMCLK Output Rise Time Output Fall Time Load Capacitance BLANK/CORBLA Output Rise Time Output Fall Time Load Capacitance Output voltage no data insertion (Video) Output voltage for data insertion Output voltage no data insertion no contrast reduction Output voltage for contrast reduction and no data insertion DC Characteristics (cont'd) Symbol Limit Values min. max. 6 6 35 5 6 6 35 5 2 2 20 12.5 12.5 20 0.5 - ns ns pF pF ns ns pF pF ns ns pF ns ns pF V V (10% - 90%) (10% - 90%) - - (10% - 90%) (10% - 90%) - - (10% - 90%) (10% - 90%) - (10% - 90%) (10% - 90%) - - - Unit Test Condition tr tf CL CI tr tf CL CI tr tf CL tr tf CL Vi-n Vi-y - - - - - - - - - - - 8 8 - 0 0.9 WR, CSSDRAM, CLKEN, LDQM, UDQM BLANK/CORBLA (Control bit CORBL = 0; BLANK only) BLANK/CORBLA (Control bit CORBL = 1; BLANK and COR) Vic-n 0 0.5 V - Vc-y 0.9 1.2 V - Users Manual 14 - 7 2000-06-15 SDA 6000 Electrical Characteristics Table 14-3 Parameter Output voltage for data insertion HSYNC Input Rise Time Input Fall Time Input Hysteresis Input Pulse Width Output Pulse Width Output Rise Time Output Fall Time Load Capacitance Pin capacitance VSYNC Input Rise Time Input Fall Time Input Hysteresis Input Pulse Width Output Pulse Width Output Rise Time Output Fall Time Load Capacitance Pin capacitance VCS Timing (Master mode) Pulse width of H-Sync Distance between Equalizing Impulses Pulse Width of Equalizing Impulses Pulse Width of Field Sync Impulses Users Manual DC Characteristics (cont'd) Symbol Limit Values min. max. - V - Unit Test Condition Vi-y 1.8 tr tf VHYST TIPWH TOPWH tr tf CL CI tr tf VHYST TIPWV TIPWV tr tf CL CI tHPVCS tDEP tEP tFSP - - 300 100 1 - - - - - - 300 2/fh 100 100 600 - 100 100 50 5 200 200 600 - 1/fH ns ns mV ns us ns ns pF pF ns ns mV - - ns ns pF pF s s s s (10% - 90%) (10% - 90%) - - - (10% - 90%) (10% - 90%) - - (10% - 90%) (10% - 90%) - - Depends on Register HPR (10% - 90%) (10% - 90%) - - - - - - - - - - 4.59 31.98 2.31 27.39 100 100 50 5 14 - 8 2000-06-15 SDA 6000 Electrical Characteristics Table 14-3 Parameter Horizontal Period P2.x, P3.x, P5.x, P6.x Output Rise Time Output Fall Time Load Capacitance Pin capacitance Input Impedance (Analog Ports) Input Sample Frequency (General Purpose Ports) Output Current (P3.10, P3.14) DC Characteristics (cont'd) Symbol Limit Values min. max. s Depends on Register HPR (10% - 90%) (10% - 90%) - - Unit Test Condition tHPR - tr tf CL CI ZP FS Io - - - - - - - - 25 25 100 10 - 33 8 100 ns ns pF pF 1/M - MHz mA mV - - - Hysteresis Voltage UHSYT 2 (I C Inputs): P6.5, P6.6, P6.7, P3.0, P3.1) Input Voltage Range ADC Resolution Output during Underflow Output during Overflow Bandwidth Sampling Time Sampling Frequency Input Source Resistance Pin capacitance (Analog Ports) Reset RSTIN Pin capacitance Reset In Pull Up Resistor Input High Voltage A/D Converter Characteristics (Port 5.0 to P5.3) Vain RES - - - 0 8 0 255 10.5 2 21 - - 2.5 V BIT - - kHz s - binary - - - - - - - tS fSAM RS CP - 100 40 kHz k pF CI Rpullup UIH - 47 2 5 100 - pF k V - - - Users Manual 14 - 9 2000-06-15 SDA 6000 Electrical Characteristics 14.4 Timings VSYNC t OPWV t OPWH HSYNC Line i Line i+1 Line i+2 UET11193 Figure 14-1 H/V - Sync-Timing (Sync-master mode) Equalizing Pulses Field Sync Pulses Equalizing Pulses VCS Horizontal Pulses Horizontal Pulse Equalizing Pulses Field Sync Pulses VCS t HPVCS t HPR t DEP t HPR t EP t FSP t HPVCS t HPR UET11194 Figure 14-2 VCS -Timing (Sync-master mode) Users Manual 14 - 10 2000-06-15 SDA 6000 Electrical Characteristics 14.5 Package Outlines P-MQFP-128-2 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Users Manual 14 - 11 Dimensions in mm 2000-06-15 GPM09233 |
Price & Availability of P-MQFP-128-2
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |